Abstract: A method of forming fine island patterns of semiconductor devices includes: forming first mask pillars on a hard mask layer on a substrate; forming an upper buffer mask layer on the hard mask layer to cover the first mask pillars; forming first linear patterns each extending along a first direction, second linear patterns each extending along a second direction, and third linear patterns each extending along a third direction in the hard mask layer by at least one patterning process; etching the upper buffer mask layer to form second mask pillars on the hard mask layer; etching an exposed portion of the hard mask layer exposed by the first mask pillars and the second mask pillars until portions of the substrate are etched; and removing the first mask pillars, the second mask pillars, and remaining portions of the hard mask layer.

Abstract: A method of forming fine island patterns of semiconductor devices includes: forming first mask pillars on a hard mask layer on a substrate; forming an upper buffer mask layer on the hard mask layer to cover the first mask pillars; forming first linear patterns each extending along a first direction, second linear patterns each extending along a second direction, and third linear patterns each extending along a third direction in the hard mask layer by at least one patterning process; etching the upper buffer mask layer to form second mask pillars on the hard mask layer; etching an exposed portion of the hard mask layer exposed by the first mask pillars and the second mask pillars until portions of the substrate are etched; and removing the first mask pillars, the second mask pillars, and remaining portions of the hard mask layer.

Abstract: A semiconductor structure includes a substrate having a memory array region and a peripheral circuit region; a plurality of first line patterns positioned in the memory array region and extending along a first direction; a plurality of second line patterns positioned over the first line patterns in the memory array region; and a plurality of linear features positioned in the peripheral circuit region. The plurality of second line patterns extend along a second direction different from the first direction. The plurality of second line patterns and the plurality of linear features are positioned at substantially the same level in the substrate.

Abstract: The present disclosure provides a semiconductor pattern and a method for preparing the same. The semiconductor pattern includes a substrate, a plurality of first semiconductor structures disposed over the substrate, a plurality of second semiconductor structures disposed over the substrate, and a semiconductor frame structure disposed over the substrate. The first semiconductor structures and the second semiconductor structures are alternately arranged. The semiconductor frame structure encircles the first semiconductor structures and the second semiconductor structures. The first semiconductor structures include a first length, the second semiconductor structures include a second length, and the first length of the first semiconductor structures is less than the second length of the second semiconductor structures.

Abstract: A method of forming fine island patterns of semiconductor devices includes: forming a plurality of first mask pillars on a hard mask layer on a substrate; forming an upper buffer mask layer on the hard mask layer to cover the first mask pillars; patterning a plurality of islands in the upper buffer mask layer; separating each of the islands into a plurality of sub-islands; etching the upper buffer mask layer to form a plurality of second mask pillars on the hard mask layer; etching an exposed portion of the hard mask layer exposed by the first mask pillars and the second mask pillars until portions of the substrate are etched; and removing the first mask pillars, the second mask pillars, and remaining portions of the hard mask layer.

Abstract: The present disclosure provide a method for preparing a semiconductor structure. The semiconductor structure includes a substrate having a memory array region and a peripheral circuit region; a plurality of first line patterns positioned in the memory array region and extending along a first direction; a plurality of second line patterns positioned over the first line patterns in the memory array region; and a plurality of linear features positioned in the peripheral circuit region. The plurality of second line patterns extend along a second direction different from the first direction. The plurality of second line patterns and the plurality of linear features are positioned at substantially the same level in the substrate.

Abstract: A method for forming a pattern includes steps of forming a patterned core layer on a substrate, conformally forming a spacer layer on the patterned core layer to form first concave portions, performing an etch back process to expose the patterned core layer, removing the exposed patterned core layer to form second concave portions, filling up the first concave portions and the second concave portions with a directed self-assembly material, and activating a directed self-assembly process, so that the directed self-assembly material is diffused to the perimeter of the concave portions to form a hole surrounding by the directed self-assembly material in each concave portions.

Abstract: A method for forming a pattern includes steps of forming a patterned core layer on a substrate, conformally forming a spacer layer on the patterned core layer to form first concave portions, performing an etch back process to expose the patterned core layer, removing the exposed patterned core layer to form second concave portions, filling up the first concave portions and the second concave portions with a directed self-assembly material, and activating a directed self-assembly process, so that the directed self-assembly material is diffused to the perimeter of the concave portions to form a hole surrounding by the directed self-assembly material in each concave portions.

Abstract: A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.

Abstract: A dynamic wafer alignment method and an exposure scanner system are provided. The exposure scanner system having a scan path, includes an exposure apparatus, an optical sensor apparatus and a wafer stage.

Abstract: An exposure method is disclosed. A wafer coated with a photoresist layer having an exposure threshold dose is provided. The wafer has at least a central region and a peripheral region. Then, a compensating light beam having a first dose directs on the photoresist layer within the peripheral region. Next, a patterned light beam having a second dose is then projected, in a step-and-scan manner, onto the photoresist layer, thereby exposing the photoresist layer. The total dose of the first energy and the second energy is above than the exposure threshold dose.

Abstract: A method of forming a ring-type capacitor is provided. The method includes providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer defining a ring pattern; removing the substrate by using the patterned mask layer as a mask to form a ring-type trench in the substrate; the ring-type trench including an inner wall and an outer wall; and forming a capacitor structure on the inner wall and the outer wall of the ring-type trench.

Abstract: An exposure method suitable for a photolithography process is described. First, a wafer with a group of alignment marks formed thereon is provided. A first alignment step is conducted by using the group of the alignment marks on the wafer to obtain a first calibration data. Next, a second alignment step is conducted by using a portion of the group of alignment marks on the wafer to obtain a second calibration data. The first calibration data is then compared with the second calibration data to obtain a comparison result. Next, a photoresist exposure step is conducted on the wafer according to the comparison result.

Abstract: An apparatus for homogenizing the developer concentration on the wafer and reducing the developer cost and the method thereof are provided in the present invention. The developer is provided on the wafer which then is spun to distribute the developer on the wafer. Next, the mechanical turbulence of the developer is produced on the wafer by the turbulence device or the mega-sonic vibrator. The apparatus is able to improve the uniformity of developer concentration, and the developer consumption is reduced.

Abstract: A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT and GC-DT overlay alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and to refresh the trench profile, thereby improving overlay alignment accuracy and precision.

Abstract: A scanning exposure method is provided. A mask and a substrate are oppositely moved along a direction. The mask and the substrate are moved in at least two different uniform relative velocities during a one shot exposure, thus producing an exposed shot area of an expected size on the substrate.

Abstract: An exposure method is disclosed. A wafer coated with a photoresist layer having an exposure threshold dose is provided. The wafer has at least a central region and a peripheral region. Then, a compensating light beam having a first dose directs on the photoresist layer within the peripheral region. Next, a patterned light beam having a second dose is then projected, in a step-and-scan manner, onto the photoresist layer, thereby exposing the photoresist layer. The total dose of the first energy and the second energy is above than the exposure threshold dose.

Abstract: A method for exposure is provided to avoid a rise in temperature of a lens set. First, a light beam passes through a first light-receiving region of the lens set to expose a pattern on a substrate, and the first light-receiving region has a rise in temperature. Thereafter, the first light-receiving region is moved away. Afterwards, the light beam passes through a second light-receiving region of the lens set so that the first light-receiving region has a drop in temperature.

Abstract: A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.

Abstract: An exposure method suitable for a photolithography process is described. First, a wafer with a group of alignment marks formed thereon is provided. A first alignment step is conducted by using the group of the alignment marks on the wafer to obtain a first calibration data. Next, a second alignment step is conducted by using a portion of the group of alignment marks on the wafer to obtain a second calibration data. The first calibration data is then compared with the second calibration data to obtain a comparison result. Next, a photoresist exposure step is conducted on the wafer according to the comparison result.