Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. The core region has an approximately square-shape cross section and a first shell of the one or more shells forms a first shell region of an approximately rhombus-shape cross section around the core region and is connected to an adjacent first shell region corresponding to a neighboring semiconductor wire.

Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire extends into the source/drain region. The semiconductor wire in the source/drain regions is wrapped around by a second semiconductor material.

Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

Abstract: The present disclosure provides devices and methods which provide for strained epitaxial regions. A method of semiconductor fabrication is provided that includes forming a gate structure over a fin of a semiconductor substrate and forming a recess in the fin adjacent the gate structure. A sidewall of the recess is then altered. Exemplary alterations include having an altered profile, treating the sidewall, and forming a layer on the sidewall. An epitaxial region is then grown in the recess. The epitaxial region interfaces the altered sidewall of the recess and is a strained epitaxial region.

Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. A mask pattern is formed over the sacrificial layer. The sacrificial layer and the source/drain structure are patterned by using the mask pattern as an etching mask, thereby forming openings adjacent to the patterned sacrificial layer and source/drain structure. A dielectric layer is formed in the openings. After the dielectric layer is formed, the patterned sacrificial layer is removed to form a contact opening over the patterned source/drain structure. A conductive layer is formed in the contact opening.

Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.

Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.

Abstract: A semiconductor device includes an n-type vertical field-effect transistor (FET) that includes: a first source/drain feature disposed in a substrate; a first vertical bar structure that includes a first sidewall and a second sidewall disposed over the substrate; a gate disposed along the first sidewall of the first vertical bar structure; a second vertical bar structure electrically coupled to the first vertical bar structure; and a second source/drain feature disposed over the first vertical bar structure; and a p-type FET that includes; a third source/drain feature disposed in the substrate; a third vertical bar structure that includes a third sidewall and a fourth sidewall disposed over the substrate; the gate disposed along the third sidewall of the third vertical bar structure; a fourth vertical bar structure electrically coupled to the third vertical bar structure; and a fourth source/drain feature disposed over the third vertical bar structure.

Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

Abstract: Epoxy/MMT composite material and a crosslinking method for epoxy/MMT composite material with second order nonlinear optical properties are introduced. Chromophore-containing intercalating agents are applied to modify montmorillonites (MMTs) to form organoclays by an ion-exchange process, wherein the chrmophores are neatly packed on exfoliated epoxy/organoclay nanocomposites. As a result, optical nonlinearity, i.e. the Pockels effect is observed for the nanocomposites without resorting to the poling process due to self-assembly process. Furthermore, a series of epoxy/MMT nanocomposites comprising thermally reversible furan-norbornene Diels-Alder adducts are prepared to establish a crosslinking feature. Self-alignment behavior, electro-optical (EO) coefficient and temporal stability of the epoxy/MMT nanocomposites are improved by the Diels-Alders crosslinking.

Abstract: A method of intelligent power distribution for a charging system with double charging terminals is provided. The method of the present invention comprises the following steps, determining whether a first vehicle is requesting for charging or not. Then, the next step is determining whether a second vehicle is charging in the system or not. If the determination is affirmative, the first vehicle is then charged by remainder power modules. In the following, it is determining whether remainder power modules can be used for a second output terminal. Subsequently, it is determining whether the first vehicle needs more power by charging. If the determination is affirmative, the remainder power modules are charging to the first vehicle via the second output terminal.

Abstract: Methods of forming semiconductor devices and structures thereof are disclosed. In some embodiments, a semiconductor device includes a substrate that includes fins. Gates are disposed over the fins, the gates being substantially perpendicular to the fins. A source/drain region is disposed on each of fins between two of the gates. A contact is coupled to the source/drain region between the two of the gates. The source/drain region comprises a first width, and the contact comprises a second width. The second width is substantially the same as the first width.

Abstract: A power supply system with automatic switchover voltage for vehicle control unit is proposed. The system comprises a supply communication module configured to communicate with a vehicle control unit, the supply communication module comprising a power supply module to provide power for a vehicle control unit; and a communication device coupled to the supply communication module for showing power supply status; wherein the supply communication module provides a first direct voltage and communicates with the vehicle control unit before supplying power, and if the supply communication module does not receive any message from the vehicle control unit within a first time interval, the supply communication module automatically switches to a second direct voltage from the first direct voltage or automatically increases the first direct voltage within a second time interval, and supplies power to the vehicle control unit; and wherein the second direct voltage is greater than the first direct voltage.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. An upper portion of the fin structure includes a first surface and a second surface which is inclined to the first surface. The semiconductor device structure also includes an isolation feature surrounding a lower portion of the fin structure. The semiconductor device structure further includes a passivation layer covering the first surface and the second surface of the upper portion. The passivation layer includes a semiconductor material and has a substantially uniform thickness. In addition, the semiconductor device structure includes an interfacial layer over the passivation layer. The interfacial layer includes the semiconductor material. The interfacial layer has a first portion covering the fin structure and a second portion covering the isolation feature.

Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

Abstract: A semiconductor device and a method of forming the semiconductor device is disclosed. A sacrificial film is used to pattern a contact to a semiconductor structure, such as a contact to a source/drain region of a transistor. The contact may include a tapered profile along an axis parallel to the gate electrode such that an outermost width of the contact decreases as the contact extends away from the source/drain region.

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Abstract: A display controller, video signal transmitting method and system thereof are provided. The display controller includes a processing circuit; a transmitting channel, coupled to the processing circuit; a receiving channel, coupled to the processing circuit; and a clock generator, that generates an internal clock signal and an external clock signal. Upon receiving a video signal, the processing circuit processes a first partial pixel data of the video signal to output a first display control signal. The transmitting channel converts a second partial pixel data of the video signal to a partial video signal having a multiple data rate according to the internal clock signal to be outputted.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a stacked wire structure formed over the substrate. The semiconductor device structure also includes a gate structure formed over a middle portion of the stacked wire structure and a source/drain (S/D) structure formed at two opposite sides of the stacked wire structure. The S/D structure includes a top surface, a sidewall surface, and a rounded corner between the top surface and the sidewall surface.

Abstract: A server, a server management system and a server management method are disclosed. The server comprises a field replaceable unit (FRU) memory and a baseboard management controller (BMC). The FRU memory stores an FRU data. The BMC receives an FRU access command from a remote management computer via an intelligent platform management interface (IPMI). The FRU access command comprises an FRU identification (ID). The BMC determines whether the FRU ID belongs to the FRU memory. If the FRU ID does not belong to the FRU memory, the BMC accesses a custom file according to the FRU ID. The custom file is different from the FRU data.