Patents by Inventor Chieh-An YEH

Chieh-An YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DUAL NITRIDE STRESSOR FOR SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING
    Publication number: 20160336319
    Abstract: A method for manufacturing a semiconductor device includes forming a fin structure over a substrate and forming a first gate structure over a first portion of the fin structure. A first nitride layer is formed over a second portion of the fin structure. The first nitride layer is exposed to ultraviolet radiation. Source/drain regions are formed at the second portion of the fin structure.
    Type: Application
    Filed: May 15, 2015
    Publication date: November 17, 2016
    Inventors: Yu-Lin YANG, Chia-Cheng HO, Chih Chieh YEH, Cheng-Yi PENG, Tsung-Lin LEE
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20160336429
    Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.
    Type: Application
    Filed: May 15, 2015
    Publication date: November 17, 2016
    Inventors: Cheng-Yi PENG, Chih Chieh YEH, Chih-Sheng CHANG, Hung-Li CHIANG, Hung-Ming CHEN, Yee-Chia YEO
  • Strain Enhancement for FinFETs
    Publication number: 20160336237
    Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.
    Type: Application
    Filed: July 27, 2016
    Publication date: November 17, 2016
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Feng Yuan, Hung-Li Chiang, Wei-Jen Lai
  • Voids in STI Regions for Forming Bulk FinFETs
    Publication number: 20160315015
    Abstract: An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at least a bottom surface of the void being defined by the one of the two insulation regions. The integrated circuit structure further includes a first semiconductor strip between and adjoining the two insulation regions, where the first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions, a gate dielectric over a top surface and sidewalls of the fin, and a gate electrode over the gate dielectric.
    Type: Application
    Filed: July 1, 2016
    Publication date: October 27, 2016
    Inventors: Hung-Ming Chen, Feng Yuan, Tsung-Lin Lee, Chih Chieh Yeh
  • Techniques for accessing a dynamic random access memory array
    Patent number: 9472249
    Abstract: Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple pages responsive to a same column address strobe. In other examples, sub-arrays of a DRAM bank may be arranged such that input/output (IO) bits may be routed in a serialized manner over an IO wire. For these other examples, the IO wire may pass through a DRAM die including the DRAM bank and/or may couple to a memory channel or bus outside of the DRAM die. Other examples are described and claimed.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: October 18, 2016
    Assignee: INTEL CORPORATION
    Inventors: Andre Schaefer, Jen-Chieh Yeh, Pei-Wen Luo
  • Semiconductor device and manufacturing method thereof
    Patent number: 9466678
    Abstract: The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, an epitaxial structure, and a recess. The epitaxial structure is disposed in the substrate. The recess is formed in the epitaxial structure, where the recess has a cross-section in a direction perpendicular to the substrate, and at least one portion of the recess is gradually expanded from an opening of the recess.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: October 11, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Hsien Huang, Che-Wei Chang, Chih-Chieh Yeh, Tzu-I Tsai
  • Metal gate finFET device
    Patent number: 9461041
    Abstract: A device including a substrate having a fin. A metal gate structure is formed on the fin. The metal gate structure includes a stress metal layer formed on the fin such that the stress metal layer extends to a first height from an STI feature, the first height being greater than the fin height. A conduction metal layer is formed on the stress metal layer.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: October 4, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lin Yang, Tsu-Hsiu Perng, Chih Chieh Yeh, Li-Shyue Lai
  • Semiconductor process and fin-shaped field effect transistor
    Patent number: 9450094
    Abstract: A semiconductor process includes the following steps. A fin on a substrate is provided. Spacers are formed only on sidewalls of the fin, where a top surface of the fin is higher than or equal to top surfaces of the spacers. An epitaxial structure is formed on the fin. The present invention also provides a fin-shaped field effect transistor including a fin, spacers and an epitaxial structure. The fin is located on a substrate. The spacers are disposed only on sidewalls of the fin, where a top surface of the fin is higher than or equal to top surfaces of the spacers. The epitaxial structure is disposed on the fin.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: September 20, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chieh Yeh, Kai-Lin Lee
  • Uninterruptible power system with backfeed detection and method of operating the same
    Patent number: 9431853
    Abstract: An uninterruptible power system and a method of operating the same are disclosed. The uninterruptible power system includes a power conversion apparatus, a switch unit, a first voltage detection unit, a second voltage detection unit, and a comparison unit. The power conversion apparatus receives an AC power source and converts the AC power source to supply an AC load. The first voltage detection unit detects an input voltage of the power conversion apparatus and produces a first voltage signal. The second voltage detection unit detects an output voltage of the switch unit and produces a second voltage signal. Under the AC power source is disabled and the power conversion apparatus provides a backup power to supply the AC load, the switch unit is detected in a fault operation when the first voltage signal is compared by the comparison unit to equal to the second voltage signal.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: August 30, 2016
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Sung-Chieh Yeh, Wei-Guo Shen, Hui Zhou, Zu-Cheng Liu
  • SEMICONDUCTOR DEVICE HAVING A STRAINED REGION
    Publication number: 20160247901
    Abstract: The present disclosure provides devices and methods which provide for strained epitaxial regions. A method of semiconductor fabrication is provided that includes forming a gate structure over a fin of a semiconductor substrate and forming a recess in the fin adjacent the gate structure. A sidewall of the recess is then altered. Exemplary alterations include having an altered profile, treating the sidewall, and forming a layer on the sidewall. An epitaxial region is then grown in the recess. The epitaxial region interfaces the altered sidewall of the recess and is a strained epitaxial region.
    Type: Application
    Filed: February 12, 2016
    Publication date: August 25, 2016
    Inventors: Feng Yuan, Chih Chieh Yeh, Hung-Li Chiang, Tsung-Lin Lee
  • FinFETs with different fin heights
    Patent number: 9425102
    Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Chang-Yun Chang, Feng Yuan
  • Strain enhancement for FinFETs
    Patent number: 9419134
    Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Feng Yuan, Hung-Li Chiang, Wei-Jen Lai
  • Gate structure for semiconductor device
    Patent number: 9397097
    Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate having a fin with a top surface and a first and second lateral sidewall. A hard mask layer may be formed on the top surface of the fin (e.g., providing a dual-gate device). A gate dielectric layer and work function metal layer are formed on the first and second lateral sidewalls of the fin. A silicide layer is formed on the work function metal layer on the first and the second lateral sidewalls of the fin. The silicide layer may be a fully-silicided layer and may provide a stress to the channel region of the device disposed in the fin.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: July 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee Lee, Feng Yuan, Chih Chieh Yeh, Wei-Jen Lai
  • Voids in STI regions for forming bulk FinFETs
    Patent number: 9385046
    Abstract: An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at least a bottom surface of the void being defined by the one of the two insulation regions. The integrated circuit structure further includes a first semiconductor strip between and adjoining the two insulation regions, where the first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions, a gate dielectric over a top surface and sidewalls of the fin, and a gate electrode over the gate dielectric.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ming Chen, Feng Yuan, Tsung-Lin Lee, Chih Chieh Yeh
  • ASYMMETRIC SOURCE/DRAIN DEPTHS
    Publication number: 20160190136
    Abstract: A semiconductor device includes a substrate having a first region and a second region, an n-type transistor in the first region, the n-type transistor comprising a first set of source/drain features, and a p-type transistor in the second region, the p-type transistor comprising a second set of source/drain features. The second set of source/drain features extend deeper than the first set of source/drain features.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 30, 2016
    Inventors: Cheng-Yi Peng, Yu-Lin Yang, Chia-Cheng Ho, Jung-Piao Chiu, Tsung-Lin Lee, Chih Chieh Yeh, Chih-Sheng Chang, Yee-Chia Yeo
  • SHORT CHANNEL EFFECT SUPPRESSION
    Publication number: 20160181244
    Abstract: A method of fabricating a semiconductor device includes forming a plurality of isolation features on a semiconductor substrate, thereby defining a first set of semiconductor features, performing an etching process on the first set of semiconductor features such that larger semiconductor features are etched deeper than smaller semiconductor features, after the etching process, forming anti-punch-through features on surfaces of the exposed features of the first set of semiconductor features, forming a semiconductor layer over the anti-punch-through features, and forming transistors on the semiconductor layer of each of the features of the first set of semiconductor features
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Inventors: Cheng-Yi Peng, Yu-Lin Yang, Chia-Cheng Ho, Hung-Li Chiang, Wei-Jen Lai, Tzu-Chiang Chen, Tsung-Lin Lee, Chih Chieh Yeh, Chih-Sheng Chang, Yee-Chia Yeo
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20160181383
    Abstract: The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, an epitaxial structure, and a recess. The epitaxial structure is disposed in the substrate. The recess is formed in the epitaxial structure, where the recess has a cross-section in a direction perpendicular to the substrate, and at least one portion of the recess is gradually expanded from an opening of the recess.
    Type: Application
    Filed: February 3, 2015
    Publication date: June 23, 2016
    Inventors: Shih-Hsien Huang, Che-Wei Chang, Chih-Chieh Yeh, Tzu-I Tsai
  • METHOD OF FORMING SEMICONDUCTOR DEVICE WITH DIFFERENT THRESHOLD VOLTAGES
    Publication number: 20160172247
    Abstract: A method for fabricating a semiconductor device includes forming a first gate stack over a first fin feature and second gate stack over a second fin feature, removing the first gate stack to form a first gate trench that exposes the first fin structure, removing the second gate stack to form a second gate trench that exposes the second fin feature, performing an annealing process to change a composition of a portion of the first fin feature and forming a first high-k/metal gate (HK/MG) within the first gate trench over the portion of the first fin feature and a second HK/MG within the second gate trench over the second fin feature. Therefore the first HK/MG is formed with a first threshold voltage and the second HK/MG is formed with a second threshold voltage, which is different than the first threshold voltage.
    Type: Application
    Filed: December 12, 2014
    Publication date: June 16, 2016
    Inventors: Chia-Cheng Ho, Cheng-Yi Peng, Chih Chieh Yeh, Tsung-Lin Lee, Jung-Piao Chiu
  • Method of Forming Semiconductor Device with Different Threshold Voltages
    Publication number: 20160172248
    Abstract: A method for fabricating a semiconductor device includes forming a first gate stack over a first fin feature and second gate stack over a second fin feature, removing the first gate stack to form a first gate trench that exposes the first fin structure, removing the second gate stack to form a second gate trench that exposes the second fin feature, performing a high-pressure-anneal process to a portion of the first fin feature and forming a first high-k/metal gate (HK/MG) within the first gate trench over the portion of the first fin feature and a second HK/MG within the second gate trench over the second fin feature. Therefore the first HK/MG is formed with a first threshold voltage and the second HK/MG is formed with a second threshold voltage, which is different than the first threshold voltage.
    Type: Application
    Filed: August 28, 2015
    Publication date: June 16, 2016
    Inventors: Cheng-Yi Peng, Chia-Cheng Ho, Chih Chieh Yeh, Tsung-Lin Lee, Yu-Lin Yang
  • Germanium FinFETs with Metal Gates and Stressors
    Publication number: 20160155668
    Abstract: An integrated circuit structure includes an n-type fin field effect transistor (FinFET) and a p-type FinFET. The n-type FinFET includes a first germanium fin over a substrate; a first gate dielectric on a top surface and sidewalls of the first germanium fin; and a first gate electrode on the first gate dielectric. The p-type FinFET includes a second germanium fin over the substrate; a second gate dielectric on a top surface and sidewalls of the second germanium fin; and a second gate electrode on the second gate dielectric. The first gate electrode and the second gate electrode are formed of a same material having a work function close to an intrinsic energy level of germanium.
    Type: Application
    Filed: January 25, 2016
    Publication date: June 2, 2016
    Inventors: Chih Chieh Yeh, Chih-Sheng Chang, Clement Hsingjen Wann