Abstract: An embodiment of a method for forming a transistor that includes providing a semiconductor substrate having a source/drain region is provided where a first SiGe layer is formed over the source/drain region. A thermal oxidation is performed to convert a top portion of the first SiGe layer to an oxide layer and a bottom portion of the first SiGe layer to a second SiGe layer. A thermal diffusion process is performed after the thermal oxidation is performed to form a SiGe area from the second SiGe layer. The SiGe area has a higher Ge concentration than the first SiGe layer.

Abstract: A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.

Abstract: FinFETs and methods of forming finFETs are described. According to some embodiments, a structure includes a channel region, first and second source/drain regions, a dielectric layer, and a gate electrode. The channel region includes semiconductor layers above a substrate. Each of the semiconductor layers is separated from neighboring ones of the semiconductor layers, and each of the semiconductor layers has first and second sidewalls. The first and second sidewalls are aligned along a first and second plane, respectively, extending perpendicularly to the substrate. The first and second source/drain regions are disposed on opposite sides of the channel region. The semiconductor layers extend from the first source/drain region to the second source/drain region. The dielectric layer contacts the first and second sidewalls of the semiconductor layers, and the dielectric layer extends into a region between the first plane and the second plane. The gate electrode is over the dielectric layer.

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a stacked wire structure formed over the substrate. The semiconductor device structure also includes a gate structure formed over a middle portion of the stacked wire structure and a source/drain (S/D) structure formed at two opposite sides of the stacked wire structure. The S/D structure includes a top surface, a sidewall surface, and a rounded corner between the top surface and the sidewall surface.

Abstract: Epoxy/MMT composite material and a crosslinking method for epoxy/MMT composite material with second order nonlinear optical properties are introduced. Chromophore-containing intercalating agents are applied to modify montmorillonites (MMTs) to form organoclays by an ion-exchange process, wherein the chrmophores are neatly packed on exfoliated epoxy/organoclay nanocomposites. As a result, optical nonlinearity, i.e. the Pockels effect is observed for the nanocomposites without resorting to the poling process due to self-assembly process. Furthermore, a series of epoxy/MMT nanocomposites comprising thermally reversible furan-norbornene Diels-Alder adducts are prepared to establish a crosslinking feature. Self-alignment behavior, electro-optical (EO) coefficient and temporal stability of the epoxy/MMT nanocomposites are improved by the Diels-Alders crosslinking.

Abstract: A method for fabricating a semiconductor device includes forming a first gate stack over a first fin feature and second gate stack over a second fin feature, removing the first gate stack to form a first gate trench that exposes the first fin structure, removing the second gate stack to form a second gate trench that exposes the second fin feature, performing a high-pressure-anneal process to a portion of the first fin feature and forming a first high-k/metal gate (HK/MG) within the first gate trench over the portion of the first fin feature and a second HK/MG within the second gate trench over the second fin feature. Therefore the first HK/MG is formed with a first threshold voltage and the second HK/MG is formed with a second threshold voltage, which is different than the first threshold voltage.

Abstract: A semiconductor device includes an n-type vertical field-effect transistor (FET) that includes: a first source/drain feature disposed in a substrate; a first vertical bar structure that includes a first sidewall and a second sidewall disposed over the substrate; a gate disposed along the first sidewall of the first vertical bar structure; a second vertical bar structure electrically coupled to the first vertical bar structure; and a second source/drain feature disposed over the first vertical bar structure; and a p-type FET that includes; a third source/drain feature disposed in the substrate; a third vertical bar structure that includes a third sidewall and a fourth sidewall disposed over the substrate; the gate disposed along the third sidewall of the third vertical bar structure; a fourth vertical bar structure electrically coupled to the third vertical bar structure; and a fourth source/drain feature disposed over the third vertical bar structure.

Abstract: An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. An upper portion of the fin structure includes a first surface and a second surface which is inclined to the first surface. The semiconductor device structure also includes an isolation feature surrounding a lower portion of the fin structure. The semiconductor device structure further includes a passivation layer covering the first surface and the second surface of the upper portion. The passivation layer includes a semiconductor material and has a substantially uniform thickness. In addition, the semiconductor device structure includes an interfacial layer over the passivation layer. The interfacial layer includes the semiconductor material. The interfacial layer has a first portion covering the fin structure and a second portion covering the isolation feature.

Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.

Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on each of the first channel layers, a gate electrode layer disposed on the gate dielectric. Each of the first channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire passes through the first source/drain region and enters into an anchor region. At the anchor region, the semiconductor wire has no gate electrode layer and no gate dielectric, and is sandwiched by a second semiconductor material.

Abstract: An integrated circuit structure includes an n-type fin field effect transistor (FinFET) and a p-type FinFET. The n-type FinFET includes a first germanium fin over a substrate; a first gate dielectric on a top surface and sidewalls of the first germanium fin; and a first gate electrode on the first gate dielectric. The p-type FinFET includes a second germanium fin over the substrate; a second gate dielectric on a top surface and sidewalls of the second germanium fin; and a second gate electrode on the second gate dielectric. The first gate electrode and the second gate electrode are formed of a same material having a work function close to an intrinsic energy level of germanium.

Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire extends into the source/drain region. The semiconductor wire in the source/drain regions is wrapped around by a second semiconductor material.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a stacked wire structure formed over the substrate. The semiconductor device structure also includes a gate structure formed over a middle portion of the stacked wire structure and a source/drain (S/D) structure formed at two opposite sides of the stacked wire structure. The S/D structure includes a top surface, a sidewall surface, and a rounded corner between the top surface and the sidewall surface.

Abstract: A method includes forming a silicon cap layer on a semiconductor fin, forming an interfacial layer over the silicon cap layer, forming a high-k gate dielectric over the interfacial layer, and forming a scavenging metal layer over the high-k gate dielectric. An anneal is then performed on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer. A filling metal is deposited over the high-k gate dielectric.

Abstract: An integrated circuit transistor structure includes a semiconductor substrate, a first SiGe layer in at least one of a source area or a drain area on the semiconductor substrate, and a channel between the source area and the drain area. The first SiGe layer has a Ge concentration of 50 percent or more.

Abstract: A method for fabricating a semiconductor device includes forming a relaxed semiconductor layer on a substrate, the substrate comprising an n-type region and a p-type region. The method further includes forming a tensile strained semiconductor layer on the relaxed semiconductor layer, etching a portion of the tensile strained semiconductor layer in the p-type region, forming a compressive strained semiconductor layer on the tensile strained semiconductor layer in the p-type region, forming a first gate in the n-type region and a second gate in the p-type region, and forming a first set of source/drain features adjacent to the first gate and a second set of source/drain features adjacent to the second gate. The second set of source/drain features are deeper than the first set of source/drain features.

Abstract: A method of semiconductor device fabrication includes providing a fin extending from a substrate and having a source/drain region and a channel region. The fin includes a first layer, a second layer over the first layer, and a third layer over the second layer. A gap is formed by removing at least a portion of the second layer from the channel region. A first material is formed in the channel region to form first and second interfacial layer portions, each at least partially wrapping around the first and third layers respectively. A second material is deposited in the channel region to form first and second high-k dielectric layer portions, each at least partially wrapping around the first and second interfacial layer portions. A metal layer including a scavenging material is formed along opposing sidewalls of the first and second high-k dielectric layer portions in the channel region.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The fin structure includes a first surface and a second surface. The first surface is inclined to the second surface. The semiconductor device structure also includes a passivation layer covering the first surface and the second surface of the fin structure. The thickness of a first portion of the passivation layer covering the first surface is substantially the same as that of a second portion of the passivation layer covering the second surface.