Patents by Inventor Chieh-An YEH

Chieh-An YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sacrificial offset protection film for a FinFET device
    Patent number: 8445340
    Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary embodiment of the method includes providing a substrate; forming a fin structure over the substrate; forming a gate structure, wherein the gate structure overlies a portion of the fin structure; forming a sacrificial-offset-protection layer over another portion of the fin structure; and thereafter performing an implantation process.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: May 21, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Feng Yuan, Chih Chieh Yeh
  • Memory controller and associated control method
    Patent number: 8412883
    Abstract: A memory controller and an associated controlling method are provided. The memory controller is connected to a memory module, and includes a FIFO buffer for receiving valid data outputted from the memory module, a write pointer for indicating written data stored in the FIFO buffer, and a read pointer for indicating read data stored in the FIFO buffer. According to the controlling method, during a CAS latency of the memory module after a read command is generated, the value of the write pointer is controlled to have the same value as that of the read pointer.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: April 2, 2013
    Assignee: MStar Semiconductor, Inc.
    Inventors: Yo-Lin Chen, Hsian-Feng Liu, Ming-Chieh Yeh
  • 3D Semiconductor Device and Method of Manufacturing Same
    Publication number: 20130075818
    Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate and a 3D structure disposed over the substrate. The semiconductor device further includes a dielectric layer disposed over the 3D structure, a WFMG layer disposed over the dielectric layer, and a gate structure disposed over the WFMG layer. The gate structure traverses the 3D structure and separates a source region and a drain region of the 3D structure. The source and drain region define a channel region therebetween. The gate structure induces a stress in the channel region.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 28, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Lin Lee, Feng Yuan, Chih Chieh Yeh, Clement Hsingjen Wann
  • Data access apparatus and associated method for accessing data using internally generated clocks
    Patent number: 8395946
    Abstract: The data access apparatus comprises a phase locked loop (PLL) and a data receiving circuit. The PLL provides a plurality of internal clocks and selecting a strobe clock from the plurality of internal clocks according to a phase selection signal. The data receiving circuit comprises a latching module, for latching of the data signal according to trigger of the strobe clock and a calibrating circuit, for generating the phase selection signal for matching the data with a predetermined data according to the plurality of internal clocks in a training mode and finally determining the phase selection signal corresponding to a preferred clock used in a normal mode.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: March 12, 2013
    Assignee: MStar Semiconductor, Inc.
    Inventors: Eer-Wen Tyan, Ming-Chieh Yeh, Yi Ling Chen
  • Full Bus Transaction Level Modeling Approach for Fast and Accurate Contention Analysis
    Publication number: 20130054854
    Abstract: The present invention presents an effective Cycle-count Accurate Transaction level (CCA-TLM) full bus modeling and simulation technique. Using the two-phase arbiter and master-slave models, an FSM-based Composite Master-Slave-pair and Arbiter Transaction (CMSAT) model is proposed for efficient and accurate dynamic simulations. This approach is particularly effective for bus architecture exploration and contention analysis of complex Multi-Processor System-on-Chip (MPSoC) designs.
    Type: Application
    Filed: February 16, 2012
    Publication date: February 28, 2013
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Mao-Lin Li, Chen-Kang Lo, Li-Chun Chen, Hong-Jie Huang, Jen-Chieh Yeh, Ren-Song Tsay
  • FinFETs with multiple Fin heights
    Patent number: 8373238
    Abstract: An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: February 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Chang-Yun Chang, Feng Yuan
  • Memory interface and adaptive data access method
    Patent number: 8370568
    Abstract: A data access method for an application circuit to access a memory. The method includes steps of: receiving a first data from the application circuit; duplicating the first data to obtain a duplicated first data; and writing the first data and the duplicated first data into the memory at continuously accessible addresses. For accessing to the first data, the first data and the duplicated first data are read from the memory in response to a rising edge and a falling edge of a data-triggering signal; and one of the first data and the duplicated first data is outputted while the other of the first data and the duplicated first data is discarded.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: February 5, 2013
    Assignee: Mstar Semiconductor, Inc.
    Inventors: Ming-Chieh Yeh, Steve Wiyi Yang
  • Systems and methods for programming a memory device
    Patent number: 8369140
    Abstract: A multi-Level Cell (MLC) can be used to store, for example, 4 bits per cell by storing two bits on each of two sides. Each side can store, e.g., four different current level states that can be determined by the number of holes injected into, e.g., nitride layer, during programming. As more holes are injected the current decreases for a given voltage. The current can be low, therefore, it can be advantageous in one embodiment to use a current amplifier. The current amplifier can be a BJT, MOS or other type of device.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: February 5, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Chieh Yeh, Wen-Jer Tsai, Yi-Ying Liao
  • ACCUMULATION TYPE FINFET, CIRCUITS AND FABRICATION METHOD THEREOF
    Publication number: 20120306002
    Abstract: This description relates to a fin field-effect-transistor (FinFET) including a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have a first type dopant, and the channel comprises at least one of a Ge, SiGe, or III-V semiconductor. The FinFET further includes a gate dielectric layer over the channel and a gate over the gate dielectric layer. The FinFET further includes a nitride spacer on the substrate adjacent the gate and an oxide layer between the nitride spacer and the gate and between the nitride spacer and the substrate.
    Type: Application
    Filed: August 14, 2012
    Publication date: December 6, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Chieh YEH, Chih-Sheng CHANG, Clement Hsingjen WANN
  • LED light source module and projection device comprising the same
    Patent number: 8282223
    Abstract: A LED light source module and a projection device comprising the same are provided. The LED light source module comprises an optical element assembly, a LED assembly and a compartment structure. The compartment structure extends from at least one side edge of the LED assembly to at least one side edge of the optical element assembly, so that the LED assembly, the optical element assembly and the compartment structure form an enclosed space corporately.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: October 9, 2012
    Assignee: Delta Electronics, Inc.
    Inventors: Tsan-Yi Lin, Yun-Chieh Yeh
  • Circuit and Method for a Three Dimensional Non-Volatile Memory
    Publication number: 20120235224
    Abstract: An architecture, circuit and method for providing a very dense, producible, non volatile FLASH memory with SONOS cells. SONOS memory cells are formed using a uniformly doped channel region. A FinFET embodiment cell is disclosed. Because the novel SONOS cells do not rely on diffused regions, the cells may be formed into a three dimensional array of cells without diffusion problems. FLASH memory arrays are formed by forming layers of NAND Flash cells in the local interconnect layers of an integrated circuit, with the metal layers forming the global bit line conductors. The three dimensional non-volatile arrays formed of the SONOS cells rely on conventional semiconductor processing. P-channel and n-channel devices may be used to form the SONOS non-volatile cells.
    Type: Application
    Filed: March 23, 2012
    Publication date: September 20, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chih Chieh Yeh
  • Accumulation type FinFET, circuits and fabrication method thereof
    Patent number: 8264032
    Abstract: A FinFET includes a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have the first type dopant. The channel includes a Ge, SiGe, or III-V semiconductor. A gate dielectric layer is located over the channel and a gate is located over the gate dielectric layer.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: September 11, 2012
    Inventors: Chih Chieh Yeh, Chih-Sheng Chang, Clement Hsingjen Wann
  • Finfets and methods for forming the same
    Patent number: 8264021
    Abstract: A Fin field effect transistor (FinFET) includes a fin-channel body over a substrate. A gate electrode is disposed over the fin-channel body. At least one source/drain (S/D) region is disposed adjacent to the fin-channel body. The at least one S/D region is substantially free from including any fin structure.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: September 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Shyue Lai, Tsz-Mei Kwok, Chih Chieh Yeh, Clement Hsingjen Wann
  • Systems and methods for programming a memory device
    Patent number: 8223553
    Abstract: A multi-Level Cell (MLC) can be used to store, for example, 4 bits per cell by storing two bits on each of two sides. Each side can store, e.g., four different current level states that can be determined by the number of holes injected into, e.g., nitride layer, during programming. As more holes are injected the current decreases for a given voltage. The current can be low, therefore, it can be advantageous in one embodiment to use a current amplifier. The current amplifier can be a BJT, MOS or other type of device.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: July 17, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih Chieh Yeh, Wen Jer Tsai, Yi Ying Liao
  • TRANSACTION LEVEL SYSTEM POWER ESTIMATION METHOD AND SYSTEM
    Publication number: 20120144216
    Abstract: A transaction level (TL) system power estimation method and system are provided. The method includes inserting at least a characteristic extractor into an electronic device of a target system. The characteristic extractor extracts at least a power characteristic of the electronic device when a TL simulation is proceeding. The power characteristic provided from the characteristic extractor is converted to at least a power consumption value by using a power model. The power consumption value is recorded into a power database, for analyzing power consumption of the whole target system. In some embodiments, the TL system power estimation method and system can be applied in the target system with dynamic power management. The TL system power estimation method and system also can be used with a high-level synthesizer to develop the power-aware electronic device in a short time.
    Type: Application
    Filed: March 7, 2011
    Publication date: June 7, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wen-Tsan Hsieh, Jen-Chieh Yeh, Hong-Jie Huang, I-Yao Chuang
  • MEMORY MODELING METHODS AND MODEL GENERATORS
    Publication number: 20120089385
    Abstract: A memory modeling method is provided. According to the memory modeling method, a memory model is provided. The memory model includes an array unit, and the array unit includes an array declaration module and a calculation module. A virtual array is defined in a storage device by the array declaration module. The virtual array is configured to simulate a real memory. Further, according to the memory modeling method, an access instruction is received, and an access operation corresponding to the access instruction is performed to the virtual array, wherein the access operation is performed with a transaction level modeling method. Then, an access time or a delay time of the access operation according to the access instruction is estimated by the calculation module.
    Type: Application
    Filed: March 25, 2011
    Publication date: April 12, 2012
    Inventors: Che-Mao HSU, Jen-Chieh YEH, Hsun-Lun HUANG
  • FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD OF MANUFACTURING SAME
    Publication number: 20120012932
    Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed on a portion of the fin structure. The gate structure traverses the fin structure and separates a source region and a drain region of the fin structure, the source and drain region defining a channel therebetween. The source and drain region of the fin structure include a strained source and drain feature. The strained source feature and the strained drain feature each include: a first portion having a first width and a first depth; and a second portion disposed below the first portion, the second portion having a second width and a second depth. The first width is greater than the second width, and the first depth is less than the second depth.
    Type: Application
    Filed: July 15, 2010
    Publication date: January 19, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsu-Hsiu Perng, Chih Chieh Yeh, Tzu-Chiang Chen, Chia-Cheng Ho, Chih-Sheng Chang
  • High precision visual field tester with unprecedented detailed results
    Patent number: 8087780
    Abstract: A visual field testing apparatus for scanning the visual field of a human eye in great detail, precision, and clarity so as to detect the smallest blind area whereby allowing users the ability of early detection of glaucoma and other eye diseases of visual loss. The apparatus is small and inexpensive so that anyone can afford to purchase it and self-test without assistance so that the user can test frequently at home which further leads to early detection of eye diseases. Because of its great precision and detail in test results, the present invention is especially useful to doctors and researchers.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: January 3, 2012
    Inventors: Hsu-Chieh Yeh, Ming-Yuan Yeh
  • Memory Sharing System and Memory Sharing Method
    Publication number: 20110314214
    Abstract: A memory sharing system includes a master control device, a slave control device and a memory device. The master control device selectively generates a clock signal to the memory device. The slave control device receives and tracks the clock signal via a delay phase locked loop (DLL) to generate and align an output signal with the clock signal. The master control device arbitrates an access right.
    Type: Application
    Filed: April 13, 2011
    Publication date: December 22, 2011
    Applicant: MSTAR SEMICONDUCTOR, INC.
    Inventors: Chunkai Derrick Wei, Po-Sung Huang, Yi Ling Chen, Ming-Chieh Yeh, Chih-Chieh Lee
  • Ink cartridge
    Patent number: 8025377
    Abstract: An ink cartridge is provided with a body, a channel module attached to the body, a plurality of first engaging parts, and a plurality of second engaging parts. The first engaging parts are arranged on one of the body and the channel module, while the second engaging parts corresponding to the first engaging parts are arranged on the other of the body and the channel module. The relative position of the body and the channel module on a two-dimension plane is substantially fixed by the engagement of the first engaging parts and the second engaging parts.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: September 27, 2011
    Assignee: International United Technology Co., Ltd.
    Inventors: Chia-Fu Wu, Francis Chee-Shuen Lee, Shih-Chieh Yeh