Abstract: A multiple-gate memory cell comprises a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes two charge trapping locations beneath each of all or some of the gates in the plurality of gates. Circuitry to conduct source and drain bias voltages to the semiconductor body near a first gate and a last gate in the series, and circuitry to conduct gate bias voltages to the plurality of gates are included. The multiple-gate memory cell includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, with charge storage locations between some or all of the gates.

Abstract: A product comprising a micromirror comprising a reflective layer and a treatment layer overlying the reflective layer, and wherein the treatment layer comprises Ti.

Abstract: An apparatus for multiple polynomial-based random number generation includes an LUT device having a plurality of polynomials established therein, a signal selection unit coupled to the LUT device and operable so as to generate a select signal that is inputted to the LUT device to thereby select at least one of the polynomials established in the LUT device, and an LFSR device coupled to the LUT device and operable so as to perform LFSR operations based on the at least one of the polynomials selected from the LUT device. A method for multiple polynomial-based random number generation includes: a) establishing the polynomials in the LUT device, b) generating the select signal to select at least one of the polynomials, and c) enabling the LFSR device to perform the corresponding LFSR operations.

Abstract: An array of memory cells with a charge trapping structure coupled in series is read, by measuring current that flows between the body region of the selected memory cell and the contact region of the selected memory cell. The charge storage state of the charge trapping structure affects the measured current.

Abstract: A string of memory cells with a charge trapping structure coupled in series is read, by measuring current that flows between the body region of the selected memory cell and the contact region of the selected memory cell. The charge storage state of the charge trapping structure affects the measured current.

Abstract: A nonvolatile memory cell with a charge trapping structure coupled in series is read, by measuring current that flows between the body region of the nonvolatile memory cell and the contact region of the nonvolatile memory cell. The charge storage state of the charge trapping structure affects the measured current.

Abstract: The present invention discloses a diagonal testing method for flash memories. The testing method regards the flash memory as several squares, and executes in the direction from top to bottom and from left to right. Each square is provided with a first diagonal in ?45 degrees from the upper left to the lower right, and a second diagonal in +45 degrees from the lower left to the upper right. The present invention is to program the cells in the first diagonal or the second diagonal, and then read the cells except the first diagonal or the second diagonal; or, program the cells except the first diagonal or the second diagonal, and then read the cells in the first diagonal or the second diagonal so as to detect the disturb fault in the flash memories and normal memory fault models.

Abstract: One embodiment of the present invention provides a system having a nonvolatile memory comprising a p type semiconductor substrate, an oxide layer over the p type semiconductor substrate, a nitride layer over the oxide layer, an additional oxide layer over the nitride layer, a gate over the additional oxide layer, two N+ junctions in the p type semiconductor layer, a source and drain respectively formed in the two N+ junctions, a first bit and a second bit in the nonvolatile memory, and accordingly at least two states of operation (i.e., erase and program) therefor. That is, one bit in the nonvolatile memory can either be in an erase state or program state. For erasing a bit, electrons are injected at the gate of the nonvolatile memory. For programming a bit, electric holes are injected or electrons are reduced for that bit.

Abstract: The disclosure relates to a method and apparatus for preventing extrusion or spiking of a metal atom from a metallization layer to other layers of a silicon wafer. In one embodiment, the method includes forming a silicon-on-ship device with a MEMS component on the substrate. The MEMS component may include one or more metal or metallic alloys. To prevent spiking from the MEMS component, the sides thereof can be coated with one ore more spacer or barrier layers. In one embodiment, oxygen plasma and thermal oxidation methods are used to deposit spacers. In another embodiment, an oxide layer is deposited over the wafer, covering the substrate and the MEMS component. Selective etching or anisotropic etching can be used to remove the oxide layer from certain regions of the MEMS and the substrate while covering the sidewalls. An amorphous silicon layer can then be deposited to cover the MEMS device.

Abstract: The invention provides a nonvolatile memory and corresponding method having an optimal memory erase function and, more particularly, a method for erasing a nonvolatile memory comprising a source, a gate, a drain, a channel and a trapping layer. The method according to a preferred embodiment of the invention generally comprises the steps of applying a non-zero gate voltage to the gate, applying a non-zero source voltage to the source, applying a non-zero drain voltage to the drain in each erase shot wherein the drain voltage is generally higher in magnitude than the source voltage, generating hot holes in the nonvolatile memory, injecting the generated hot holes in the trapping layer near drain junction, and accordingly erasing the nonvolatile memory.

Abstract: A method of programming the memory cell comprises setting the memory cell to an initial state of a first gate threshold voltage, performing a processing sequence including: applying a voltage bias between the gate and the first junction region to cause electric hole to migrate towards and be retained in the trapping layer, and evaluating a read current generated in response to the voltage bias to determine whether a second gate threshold voltage is reached, wherein the second gate threshold voltage is lower than the first gate threshold voltage. The processing sequence is repeated a number of times by varying one or more time the voltage bias between the gate and the first junction region until the second gate threshold voltage is reached and the memory cell is in a program state.

Abstract: A handover method used in a wireless communication system for handing over a mobile device from a first base station to a second base station is provided. Firstly, a first signal power between the mobile device and the first base station as well as a second signal power between the mobile device and the second base station are respectively measured by the mobile device. Next, the first signal power is compared with the second signal power, and an equal signal power is generated if the two signal powers are substantially the same. Then, the mobile device is handed over to the second base band if the signal power between the mobile device and the first base station is measured by the mobile device to have the same level with the equal signal power.

Abstract: A NAND-type erasable programmable read only memory (EEPROM) device formed of a number of substantially identical EEPROM cells with each EEPROM cell being capable of storing two bits of information. A simple method for operating the memory comprises erasing, programming, and reading the device.

Abstract: A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.

Abstract: A method for programming a non-volatile memory is described. In the method, a reference level is selected according to the level distribution of the memory cells in a storage state, and then predetermined memory cells are programmed to a next storage state according to the reference level. The reference level falls between the cell level distribution of the storage state and that of the next storage state.

Abstract: A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.

Abstract: A method includes setting a plurality of predetermined stops in a line buffer of a port engine, writing a data set into the port engine, and checking the priority of a next service request after outputting data of the data set. A control device is coupled to a display device and memory for controlling the display device. The control device includes a plurality of input port engines, a plurality of output port engines, and a memory interface unit. Each input port engine includes a corresponding line buffer. The memory interface unit is coupled to the memory, the plurality of input port engines, and the plurality of output port engines, and transfer data between the output port engines, the memory and the output port engines. Data with the lowest priority is written inconsecutively into the memory based on a service length.

Abstract: To reduce the disturbance between adjacent memory cells, an improved ONO flash memory array is implanted with a pocket on one side of the channel of each memory cell or two pockets of different concentrations on both sides of the channel, thereby resulting in memory cells with asymmetric pockets. Consequently, no disturbances occurred between adjacent memory cells when the ONO flash memory array is programmed or erased by band-to-band techniques, and the disturbances between adjacent memory cells are also suppressed during reading process.

Abstract: A method of operating a non-volatile memory cell, wherein the non-volatile memory cell includes a word line, a first bit line, and a second bit line, the method includes programming the memory cell that includes applying a high positive bias to the first bit line, applying a ground bias to the second bit line, and applying a high negative bias to the word line, wherein positively-charged holes tunnel through the dielectric layer into the trapping layer.

Abstract: A cold cathode fluorescent lamp. The cold cathode fluorescent lamp includes a transparent tube, at least one absorptive structure and at least one absorptive layer. The transparent tube is filled with a gas including a material capable of arousing light by means, of an electric potential. The absorptive structure is disposed on one end of the transparent tube and includes a supporting mechanism having at least one opening. The absorptive layer is formed in the opening and is not filled with the opening.