Abstract: A method of reducing gate disturb in a charge-trapping layer memory cell by applying different Vpass voltages to different sides of a selected wordline. A higher Vpass voltage is used to pass higher source/drain voltage and a lower Vpass voltage is used to pass a lower source/drain voltage. By controlling the Vpass voltages on different sides of a selected wordline, it is possible to reduce a vertical field that is established in a gate region when the Vpass voltages are applied. A reduced vertical field results in suppressed gate disturb. The method also includes a novel bit-line biasing scheme that may further reduce the vertical field and thereby may further suppress gate disturb, particularly in an array of memory cells.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A control button assembly mounted in the top side of a mechanical pen and linked to the mechanical mechanism of the mechanical pen is disclosed to include a base member coupled to the mechanical mechanism of the mechanical pen, a cap capped on the base member for pressing by the user to drive the mechanical mechanism to move a writing tip in and out of the bottom side of the mechanical pen, a tip member threaded onto the base member inside the cap and having two longitudinal side rails respectively coupled to respective longitudinal sliding grooves inside the cap and usable as a touch pen and movable in and out of the cap upon rotary motion of the cap.

Abstract: A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: Methods and apparatuses for causing electroluminescence with charge trapping structures are disclosed. Various embodiments relate to methods and apparatuses for causing electroluminescence with charge carriers of one type provided to the charge trapping structure by a forward biased p-n structure or a reverse biased p-n structure.

Abstract: Charge trapping memory cells are protected from over-erasing in response to an erase command. For example, in response to an erase command, one bias arrangement is applied to program charge trapping memory cells, and another bias arrangement is applied to erase the charge trapping memory cells, such that the charge trapping memory cells have a higher net electron charge in the erased state than in the programmed state. In another example, an integrated circuit with an array of charge trapping memory cells has logic which responds to an erase command by applying similar bias arrangements to the charge trapping memory cells. In a further example, such an integrated circuit is manufactured.

Abstract: A multiple-gate memory cell comprises a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes charge trapping locations beneath gates in the plurality of gates. Circuitry to conduct source and drain bias voltages to the semiconductor body near a first gate and a last gate in the series, and circuitry to conduct gate bias voltages to the plurality of gates are included. The multiple-gate memory cell includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, with charge storage locations between some or all of the gates.

Abstract: In some embodiments, a memory integrated circuit has different shallow trench isolation structures in the memory circuitry of the memory integrated circuit and the control circuitry of the memory integrated circuit. The isolation dielectric fills the trenches of the shallow trench isolation structures to different degrees. In some embodiments, a memory integrated circuit has memory circuitry with shallow trench isolation structures and intermediate regions. The memory circuitry supports a channel between neighboring nonvolatile memory devices supporting multiple current components with different orientations. In some embodiments, recessed shallow trench isolation structures are formed.

Abstract: A circuit of non-volatile memory which includes a plurality of memory units is disclosed. The memory unit comprises a first switch, a second switch, a data line, a voltage storage component, and a plurality of memory components connected in series. The first terminal of the first switch is coupled to the first voltage. The data line is coupled to the second terminal of the first switch. The first terminal of the voltage storage component is coupled to the data line, and the second terminal of the voltage storage component is coupled to the ground. The first terminal of the second switch is coupled the data line. In addition, the third terminal of each memory component is coupled to the first terminal of the next memory component, and the second terminal of the each memory component is coupled to second voltage.

Abstract: A method for programming a memory cell is based on applying stress to a memory cell, comprising a first electrode, a second electrode and an inter-electrode layer, to induce a progressive change in a property of the inter-electrode layer. The method includes a verify step including generating a signal, such as a cell current, indicating the value of the property in the selected memory cell. Then, the signal is compared with a reference signal to verify programming of the desired data. Because of the progressive nature of the change, many levels of programming can be achieved. The many levels of programming can be applied for programming a single cell more than once, without an erase process, to programming multiple bits in a single cell, and to a combination of multiple bit and multiple time of programming.

Abstract: A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.

Abstract: A string of memory cells with a charge trapping structure is read, by selecting part of a memory cell selected by a word line. Part of the memory cell is selected by turning on one of the pass transistors on either side of the string of memory cells. The charge storage state of the selected part is determined by measuring current in a bit line tied to both pass transistors.

Abstract: A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.

Abstract: A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.

Abstract: Programming nonvolatile memory cells is affected by the program disturb effect which causes data accuracy issues with nonvolatile memory. Rather than masking the voltage conditions that cause the program disturb effect, voltages are applied to neighboring nonvolatile memory cells, which takes advantage of the program disturb effect to program multiple cells quickly.

Abstract: A nonvolatile memory cell with a charge trapping structure coupled in series is read, by measuring current that flows between the body region of the nonvolatile memory cell and the contact region of the nonvolatile memory cell. The charge storage state of the charge trapping structure affects the measured current.

Abstract: A fastening device for a heat sink, for being combined to each of two sides of a base of the heat sink for fastening the heat sink on an installing face is disclosed, wherein the two sides of the base respectively include jointing holes. The fastening device has at least a body, a positioning portion provided at the bottom of the body and a spiral fastening portion provided on the body to be combined with the base via spiral fastening components. Since the heat sink can be fastened via two of the fastening devices in conjunction with the spiral fastening components, problems in the prior art, such as complicated structure, excessive amount of components used and extra usage space required, can be solved.

Abstract: An array of multiple-gate memory cells includes sectors. The sectors include at least one row of multiple-gate memory cells. The multiple-gate memory cells comprise a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes charge trapping locations beneath each of all or some of the gates in the plurality of gates. Word lines and bit lines source and drain bias voltages to the semiconductor body near a first gate and a last gate in the series, and to the plurality of gates are included. The multiple-gate memory cell includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, with charge storage locations between some or all of the gates. Sector select lines are included to couple selected sectors to the bit lines.