Abstract: A NAND type multi-bit charge storage memory array comprises a first and a second memory strings each of which includes one or more charge storage memory cells and two select transistors. The charge storage memory cells are connected in series to form a memory cell string. The two select transistors are connected in series to both ends of the memory cell string, respectively. The NAND type multi-bit charge storage memory array further comprises a shared bit line and a first and a second bit lines. The shared bit line is connected with the first ends of the first and the second memory strings. The first and the second bit lines are connected to the second ends of the first and the second memory strings, respectively. The first select transistor and the second select transistor of each memory string are controlled by a first and a second select transistor control lines, respectively.

Abstract: Input habit determination and interface provision systems and methods are provided. First, a movement on a touch-sensitive surface is detected by a touch-sensitive sensor. An input habit is determined according to the movement. Then, a first interface or a second interface is selected for provision from an interface group according to the input habit. The first interface and the second interface have the same operational selections, but have different layout designs.

Abstract: A CMOS FinFET semiconductor device provides an NMOS FinFET device that includes a compressive stress metal gate layer over semiconductor fins and a PMOS FinFET device that includes a tensile stress metal gate layer over semiconductor fins. A process for forming the same includes a selective annealing process that selectively converts a compressive metal gate film formed over the PMOS device to the tensile stress metal gate film.

Abstract: The invention provides a programming system comprising a software component, a client side, and N expanding module. The software component comprises a receiving/processing interface and N first link interface; the client side could be used for transferring client information to the software component through the receiving/processing interface; and each expanding module is corresponding to one of the first link interface and comprises an expanding content. Accordingly, a connecting relation could be built between the software component and one expanding module, corresponding to the client information, of the N expanding module through the first link module, so that the software component can communicate with the expanding module to obtain the expanding content.

Abstract: A fastening structure for an expansion card is provided. The card has a baffle and one end of the baffle is formed with a bending portion and a first long hole. The fastening structure includes a flat plate located at one side of a case and has a plane extending toward inside the case; a first supporting portion and a second supporting portion fastened at the plane of the flat plate; a fastening member having a pressing portion and at least one second long hole. The fastening member is disposed at the first supporting portion via the second long hole, and slidably leans against the plane. The pressing portion extends toward the bending portion. When the fastening member slides to a fixing position, the pressing portion presses the bending portion, and the baffle is fastened at the second supporting portion via the first long hole and leans against the plane.

Abstract: A memory integrated circuit has memory arrays that are vertically layered. These memory arrays include word lines and bit lines. Intersections between the word lines and the bit lines include a diode and a memory state storage element. The diode and the memory storage element are connected in between a word line and a bit line. The diode at the intersections includes a first diode node and a second diode node. Various aspects of the memory integrated circuit are electrically interconnected in various ways, such as corresponding word lines, corresponding first diode nodes, or corresponding second diode nodes of different memory arrays being electrically interconnected. Various aspects of the memory integrated circuit are isolated in various ways, such as word lines, first diode nodes, or second diode nodes of different memory arrays being isolated.

Abstract: A fastening structure for an expansion card is provided. The card has a baffle and one end of the baffle is formed with a bending portion and a first long hole. The fastening structure includes a flat plate located at one side of a case and has a plane extending toward inside the case; a first supporting portion and a second supporting portion fastened at the plane of the flat plate; a fastening member having a pressing portion and at least one second long hole. The fastening member is disposed at the first supporting portion via the second long hole, and slidably leans against the plane. The pressing portion extends toward the bending portion. When the fastening member slides to a fixing position, the pressing portion presses the bending portion, and the baffle is fastened at the second supporting portion via the first long hole and leans against the plane.

Abstract: A handover method used in a wireless communication system for handing over a mobile device from a first base station to a second base station is provided. Firstly, a first signal power between the mobile device and the first base station as well as a second signal power between the mobile device and the second base station are respectively measured by the mobile device. Next, the first signal power is compared with the second signal power, and an equal signal power is generated if the two signal powers are substantially the same. Then, the mobile device is handed over to the second base band if the signal power between the mobile device and the first base station is measured by the mobile device to have the same level with the equal signal power.

Abstract: In some embodiments, a memory integrated circuit has different shallow trench isolation structures in the memory circuitry of the memory integrated circuit and the control circuitry of the memory integrated circuit. The isolation dielectric fills the trenches of the shallow trench isolation structures to different degrees. In some embodiments, a memory integrated circuit has memory circuitry with shallow trench isolation structures and intermediate regions. The memory circuitry supports a channel between neighboring nonvolatile memory devices supporting multiple current components with different orientations. In some embodiments, recessed shallow trench isolation structures are formed.

Abstract: A clamping device (100) for clamping a data cable (60) with a plug includes: a clamping unit (10), a limitation cabinet (20) and a plurality of elastic elements (40). The clamping unit defines a receiving groove (115) configured for receiving the plug of the data cable. The limitation cabinet defines a cavity. The clamping unit is disposed in the cavity, and is spaced apart from the limitation cabinet. The elastic elements are disposed between the clamping unit and the limitation cabinet.

Abstract: A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.

Abstract: In some embodiments, a memory integrated circuit has different shallow trench isolation structures in the memory circuitry of the memory integrated circuit and the control circuitry of the memory integrated circuit. The isolation dielectric fills the trenches of the shallow trench isolation structures to different degrees. In some embodiments, a memory integrated circuit has memory circuitry with shallow trench isolation structures and intermediate regions. The memory circuitry supports a channel between neighboring nonvolatile memory devices supporting multiple current components with different orientations. In some embodiments, recessed shallow trench isolation structures are formed.

Abstract: A memory integrated circuit has memory arrays that are vertically layered. These memory arrays include word lines and bit lines. Intersections between the word lines and the bit lines include a diode and a memory state storage element. The diode and the memory storage element are connected in between a word line and a bit line. The diode at the intersections includes a first diode node and a second diode node. Various aspects of the memory integrated circuit are electrically interconnected in various ways, such as corresponding word lines, corresponding first diode nodes, or corresponding second diode nodes of different memory arrays being electrically interconnected. Various aspects of the memory integrated circuit are isolated in various ways, such as word lines, first diode nodes, or second diode nodes of different memory arrays being isolated.

Abstract: A method for manufacturing a multiple-gate memory cell which comprises a semiconductor body and a plurality of gates arranged in series and the semiconductor body includes first forming a plurality of gates spaced apart by about a gate width, forming an isolation layer on the sidewalls, and filling between the first plurality of gates to form a second plurality of gates. A charge storage structure is formed on the semiconductor body beneath each of all or some of the gates in the plurality of gates. Circuitry is formed to conduct source and drain bias voltages to the semiconductor body near a first gate and a last gate in the series, and circuitry to conduct gate bias voltages to the plurality of gates is included. The multiple-gate memory cell includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, with charge storage locations between some or all of the gates.

Abstract: Charge trapping memory cells are protected from over-erasing in response to an erase command. For example, in response to an erase command, one bias arrangement is applied to program charge trapping memory cells, and another bias arrangement is applied to erase the charge trapping memory cells, such that the charge trapping memory cells have a higher net electron charge, in the erased state than i.n the programmed state. In another example, an integrated circuit with an array of charge trapping memory cells has logic which responds to an erase command by applying similar bias arrangements to the charge trapping memory cells. In a further example, such an integrated circuit is manufactured.

Abstract: A memory cell with a charge trapping structure is read by measuring current between the substrate region of the memory cell and one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the charge trapping structure when other parts of the charge trapping structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: An architecture, circuit and method for providing a very dense, producible, non volatile FLASH memory with SONOS cells. Preferred SONOS memory cells are formed using a uniformly doped channel region. A FinFET embodiment and a planar FD-SOI embodiment cell are disclosed. Because the novel SONOS cells do not rely on diffused regions, the cells may be formed into a three dimensional array of cells without diffusion problems from subsequent thermal processing steps. FLASH memory arrays are formed by forming layers of NAND Flash cells in the local interconnect layers of an integrated circuit, with the metal layers forming the global bit line conductors. The three dimensional non volatile arrays formed of the SONOS cells rely on conventional semiconductor processing and so are easily integrated with other circuitry to form an ASIC or SoC device. P-channel and n-channel devices may be used to form the SONOS non-volatile cells.

Abstract: Methods and apparatuses for causing electroluminescence with charge trapping structures are disclosed. Various embodiments relate to methods and apparatuses for causing electroluminescence with charge carriers of one type provided to the charge trapping structure by a forward biased p-n structure or a reverse biased p-n structure.