Patents by Inventor Chieh-An YEH

Chieh-An YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD OF SENSING MOTION IN THREE-DIMENSIONAL SPACE
    Publication number: 20110181505
    Abstract: An accelerometer and a gyroscope are disposed in a device. When the device rotates in a 3D space, angle of the device relative to gravity is calculated, movement of the device relative to gravity is calculated during the rotation process, and a real trace of the device is obtained in the 3D space.
    Type: Application
    Filed: March 29, 2010
    Publication date: July 28, 2011
    Inventors: Kui-Chang Tseng, Yi-Hsun Hsieh, Ren-Yuan Yu, Hao-Chieh Yeh
  • METAL GATE STRESS FILM FOR MOBILITY ENHANCEMENT IN FinFET DEVICE
    Publication number: 20110169085
    Abstract: A CMOS FinFET semiconductor device provides an NMOS FinFET device that includes a compressive stress metal gate layer over semiconductor fins and a PMOS FinFET device that includes a tensile stress metal gate layer over semiconductor fins. A process for forming the same includes a selective annealing process that selectively converts a compressive metal gate film formed over the PMOS device to the tensile stress metal gate film.
    Type: Application
    Filed: March 4, 2011
    Publication date: July 14, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jeff J. Xu, Clement H. Wann, Chi Chieh Yeh, Chi-Sheng Chang
  • Data Access Apparatus and Associated Method for Accessing Data Using Internally Generated Clocks
    Publication number: 20110158005
    Abstract: The data access apparatus comprises a phase locked loop (PLL) and a data receiving circuit. The PLL provides a plurality of internal clocks and selecting a strobe clock from the plurality of internal clocks according to a phase selection signal. The data receiving circuit comprises a latching module, for latching of the data signal according to trigger of the strobe clock and a calibrating circuit, for generating the phase selection signal for matching the data with a predetermined data at the plurality of internal clocks in a training mode and finally determining the phase selection signal corresponding to a preferred clock used in a normal mode.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 30, 2011
    Applicant: MSTAR SEMICONDUCTOR, INC.
    Inventors: Eer-Wen Tyan, Ming-Chieh Yeh, Yi Ling Chen
  • Memory Controller and Associated Control Method
    Publication number: 20110153963
    Abstract: A memory controller and an associated controlling method are provided. The memory controller is connected to a memory module, and includes a FIFO buffer for receiving valid data outputted from the memory module, a write pointer for indicating written data stored in the FIFO buffer, and a read pointer for indicating read data stored in the FIFO buffer. According to the controlling method, during a CAS latency of the memory module after a read command is generated, the value of the write pointer is controlled to have the same value as that of the read pointer.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 23, 2011
    Applicant: MSTAR SEMICONDUCTOR, INC.
    Inventors: Yo-Lin Chen, Hsian-Feng Liu, Ming-Chieh Yeh
  • FinFETs with Multiple Fin Heights
    Publication number: 20110133292
    Abstract: An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces.
    Type: Application
    Filed: July 26, 2010
    Publication date: June 9, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Chang-Yun Chang, Feng Yuan
  • Apparatus and Method of Generating Universal Memory I/O
    Publication number: 20110131354
    Abstract: A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function.
    Type: Application
    Filed: November 17, 2010
    Publication date: June 2, 2011
    Applicant: MSTAR SEMICONDUCTOR, INC.
    Inventors: Sterling Smith, Hsian-Feng Liu, Eer-Wen Tyan, Chun-Chia Chen, Ming-Chieh Yeh, Chung-Ching Chen, Yo-Lin Chen
  • SACRIFICIAL OFFSET PROTECTION FILM FOR A FINFET DEVICE
    Publication number: 20110117679
    Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary embodiment of the method includes providing a substrate; forming a fin structure over the substrate; forming a gate structure, wherein the gate structure overlies a portion of the fin structure; forming a sacrificial-offset-protection layer over another portion of the fin structure; and thereafter performing an implantation process.
    Type: Application
    Filed: November 19, 2009
    Publication date: May 19, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Lin Lee, Feng Yuan, Chih Chieh Yeh
  • FinFET Design with Reduced Current Crowding
    Publication number: 20110095378
    Abstract: An integrated circuit structure includes a substrate and a fin field-effect transistor (FinFET). The FinFET includes a fin over the substrate and having a first fin portion and a second fin portion. A gate stack is formed on a top surface and sidewalls of the first fin portion. An epitaxial semiconductor layer has a first portion formed directly over the second fin portion, and a second portion formed on sidewalls of the second fin portion. A silicide layer is formed on the epitaxial semiconductor layer. A peripheral ratio of a total length of an effective silicide peripheral of the FinFET to a total length of a fin peripheral of the FinFET is greater than 1.
    Type: Application
    Filed: July 23, 2010
    Publication date: April 28, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh
  • FINFETS AND METHODS FOR FORMING THE SAME
    Publication number: 20110079829
    Abstract: A Fin field effect transistor (FinFET) includes a fin-channel body over a substrate. A gate electrode is disposed over the fin-channel body. At least one source/drain (S/D) region is disposed adjacent to the fin-channel body. The at least one S/D region is substantially free from including any fin structure.
    Type: Application
    Filed: April 16, 2010
    Publication date: April 7, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Shyue LAI, Tsz-Mei KWOK, Chih Chieh YEH, Clement Hsingjen WANN
  • I/O Circuit Calibration Method and Associated Apparatus
    Publication number: 20110074520
    Abstract: An I/O calibration method and an apparatus are provided for calibrating a driving impedance at an output end of an I/O circuit in a chip. The chip further includes a plurality of basic impedances and a non-volatile memory. The I/O circuit calibration method includes: measuring an impedance value of one basic impedance and recording the measured impedance value in the non-volatile memory; synthesizing a calibration impedance by selectively conducting the basic impedance(s); adjusting the number of the conducted basic impedance(s) in the calibration impedance and estimating an impedance value of the driving impedance according to the measured result and a voltage divided by the calibration impedance and the driving impedance at the output end.
    Type: Application
    Filed: September 23, 2010
    Publication date: March 31, 2011
    Applicant: MSTAR SEMICONDUCTOR, INC.
    Inventors: Eer-Wen Tyan, Ming-Chieh Yeh
  • Metal gate stress film for mobility enhancement in FinFET device
    Patent number: 7915112
    Abstract: A CMOS FinFET semiconductor device provides an NMOS FinFET device that includes a compressive stress metal gate layer over semiconductor fins and a PMOS FinFET device that includes a tensile stress metal gate layer over semiconductor fins. A process for forming the same includes a selective annealing process that selectively converts a compressive metal gate film formed over the PMOS device to the tensile stress metal gate film.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: March 29, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeff J. Xu, Clement H. Wann, Chi Chieh Yeh, Chi-Sheng Chang
  • Germanium FinFETs with Metal Gates and Stressors
    Publication number: 20110068407
    Abstract: An integrated circuit structure includes an n-type fin field effect transistor (FinFET) and a p-type FinFET. The n-type FinFET includes a first germanium fin over a substrate; a first gate dielectric on a top surface and sidewalls of the first germanium fin; and a first gate electrode on the first gate dielectric. The p-type FinFET includes a second germanium fin over the substrate; a second gate dielectric on a top surface and sidewalls of the second germanium fin; and a second gate electrode on the second gate dielectric. The first gate electrode and the second gate electrode are formed of a same material having a work function close to an intrinsic energy level of germanium.
    Type: Application
    Filed: July 7, 2010
    Publication date: March 24, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih Chieh Yeh, Chih-Sheng Chang, Clement Hsingjen Wann
  • ACCUMULATION TYPE FINFET, CIRCUITS AND FABRICATION METHOD THEREOF
    Publication number: 20110049613
    Abstract: A FinFET includes a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have the first type dopant. The channel includes a Ge, SiGe, or III-V semiconductor. A gate dielectric layer is located over the channel and a gate is located over the gate dielectric layer.
    Type: Application
    Filed: April 9, 2010
    Publication date: March 3, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Chieh YEH, Chih-Sheng CHANG, Clement Hsingjen WANN
  • Gated diode nonvolatile memory process
    Patent number: 7888707
    Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: February 15, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Yi Ying Liao, Wen Jer Tsai, Chih Chieh Yeh
  • METHOD FOR FORMING HIGH GERMANIUM CONCENTRATION SIGE STRESSOR
    Publication number: 20110024804
    Abstract: A method for producing a SiGe stressor with high Ge concentration is provided. The method includes providing a semiconductor substrate with a source area, a drain area, and a channel in between; depositing the first SiGe film layer on the source area and/or the drain area; performing a low temperature thermal oxidation, e.g., a high water vapor pressure wet oxidation, to form an oxide layer at the top of the first SiGe layer and to form the second SiGe film layer with high Ge percentage at the bottom of the first SiGe film layer without Ge diffusion into the semiconductor substrate; performing a thermal diffusion to form the SiGe stressor from the second SiGe film layer, wherein the SiGe stressor provides uniaxial compressive strain on the channel; and removing the oxide layer. A Si cap layer can be deposited on the first SiGe film layer prior to performing oxidation.
    Type: Application
    Filed: July 7, 2010
    Publication date: February 3, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hao CHANG, Jeff J. XU, Chien-Hsun WANG, Chih Chieh YEH, Chih-Hsiang CHANG
  • METHOD FOR VALIDATING FEATURES IN A DIRECT MODELING PARADIGM
    Publication number: 20110025688
    Abstract: A CAD system enables a designer to freely modify a model of a design without regenerating a history of the model, as in traditional parametric feature based modeling. The CAD system automatically determines whether the modifications to the model invalidate current features associated with the model and whether the modifications create new features that should be added to the model. Such a CAD system enables a designer to quickly edit designs and simultaneously preserve design intent without requiring the significant computational resources of historical based approaches that regenerate a geometry upon every edit made by a designer.
    Type: Application
    Filed: July 28, 2009
    Publication date: February 3, 2011
    Inventors: Kevin Schneider, Rahul Vora, Jeffrey Thomas Strater, Shu-Chieh Yeh
  • Display Controller, Video Signal Transmitting Method and System
    Publication number: 20110001768
    Abstract: A display controller, video signal transmitting method and system thereof are provided. The display controller includes a processing circuit; a transmitting channel, coupled to the processing circuit; a receiving channel, coupled to the processing circuit; and a clock generator, that generates an internal clock signal and an external clock signal. Upon receiving a video signal, the processing circuit processes a first partial pixel data of the video signal to output a first display control signal. The transmitting channel converts a second partial pixel data of the video signal to a partial video signal having a multiple data rate according to the internal clock signal to be outputted.
    Type: Application
    Filed: June 24, 2010
    Publication date: January 6, 2011
    Applicant: MSTAR SEMICONDUCTOR, INC.
    Inventors: Chen-Nan Lin, Ming-Chieh Yeh, Chun Wen Yeh, Chun-Chia Chen
  • Method for Processing On-Screen Display and Associated Embedded System
    Publication number: 20100321575
    Abstract: An embedded system for processing an on-screen display (OSD) includes an input apparatus, a user interface resource storage unit and a two-dimensional (2D) graphic engine. The method for processing the OSD includes receiving a control command associated with a 2D image processing procedure, the 2D image processing procedure generating a transitional image according to a first 2D image and a second 2D image, and displaying the first 2D image, the transitional image and the second 2D image to render a three-dimensional-like (3D-like) OSD.
    Type: Application
    Filed: June 18, 2010
    Publication date: December 23, 2010
    Applicant: MStar Semiconductor, Inc.
    Inventors: TZUKUI HUANG, Chien-You Chen, Ching Ju Ko, Meng Chieh Yeh, Cheng Hao Li
  • LED LIGHT SOURCE MODULE AND PROJECTION DEVICE COMPRISING THE SAME
    Publication number: 20100309437
    Abstract: A LED light source module and a projection device comprising the same are provided. The LED light source module comprises an optical element assembly, a LED assembly and a compartment structure. The compartment structure extends from at least one side edge of the LED assembly to at least one side edge of the optical element assembly, so that the LED assembly, the optical element assembly and the compartment structure form an enclosed space corporately.
    Type: Application
    Filed: June 4, 2010
    Publication date: December 9, 2010
    Applicant: DELTA ELECTRONICS, INC.
    Inventors: Tsan-Yi LIN, Yun-Chieh YEH
  • Recessed shallow trench isolation
    Patent number: 7804152
    Abstract: In some embodiments, a memory integrated circuit has different shallow trench isolation structures in the memory circuitry of the memory integrated circuit and the control circuitry of the memory integrated circuit. The isolation dielectric fills the trenches of the shallow trench isolation structures to different degrees. In some embodiments, a memory integrated circuit has memory circuitry with shallow trench isolation structures and intermediate regions. The memory circuitry supports a channel between neighboring nonvolatile memory devices supporting multiple current components with different orientations. In some embodiments, recessed shallow trench isolation structures are formed.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: September 28, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih Chieh Yeh, Wen Jer Tsai