Abstract: A display device includes a first substrate, a light-emitting element, a light conversion layer, and a color filter layer. The light-emitting element is disposed on the first substrate. The light conversion layer is disposed on the light-emitting element. In addition, the color filter layer is overlapped the light-emitting element and the light conversion layer.

Abstract: A method for manufacturing a distributed Bragg reflector is provided. The distributed Bragg reflector is applied to a 1550 nm vertical-cavity surface-emitting laser, which structurally includes a top distributed Bragg reflector, a bottom distributed Bragg reflector, and a vertical cavity (including a P-type and an N-type electrode) and a multiple quantum well light-emitting layer that are positioned therebetween. An optical multilayer film of the distributed Bragg reflector is formed by sputtering, and includes silicon layers and silicon dioxide layers alternately stacked to each other. The silicon dioxide layers are produced by a process of nano-sputtering and micro-plasma oxidation. A reflectance of the bottom distributed Bragg reflector at 1,550 nm is greater than 99.9%, and a reflectance of the top distributed Bragg reflector at 1,550 nm is controlled to be between 95% and 99%, so that basic physical/optical requirements for forming a resonant laser can be improved.

Abstract: The present disclosure provides a method for fabricating an image sensor. The method includes the following operations. A cavity is formed at a first surface of a substrate. A germanium layer is formed in the cavity. A first heavily doped region is formed in the germanium layer by an implantation operation. A second heavily doped region is formed at a position proximal to a top surface of the germanium layer, wherein the second heavily doped region is laterally surrounded by the first heavily doped region from a top view perspective. An interconnect structure is formed over the germanium layer.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. A silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.

Abstract: A container feeding device includes a casing and first and second latch members. The casing defines a lower retaining space for receiving a plurality of containers that are stacked on one another. The first latch member is operable to enter the lower retaining space for supporting a bottommost container, or leave the lower retaining space to release the bottommost container. The second latch member enters the lower retaining space to support a second bottommost container when the bottommost container is released by the first latch member.

Abstract: A tool set includes a tool holder, a tool and a tool rack. The tool has a groove unit. The tool holder has a latch unit that engages the groove unit. The tool rack includes a rack body and a blocking member. When the tool holder is moved away from the rack body after the tool is moved into the rack body by the tool holder and after the blocking member moves to a blocking position, the tool is blocked by the blocking member so that the latch unit is separated from the groove unit and that the tool holder is separated from the tool.

Abstract: A physical analysis method, a sample for physical analysis and a preparing method thereof are provided. The preparing method of the sample for physical analysis includes: providing a sample to be inspected; and forming a contrast enhancement layer on a surface of the sample to be inspected. The contrast enhancement layer includes a plurality of first material layers and a plurality of second material layers stacked upon one another. The first material layer and the second material layer are made of different materials. Each one of the first and second material layers has a thickness that does not exceed 0.1 nm. In an image captured by an electron microscope, a difference between an average grayscale value of a surface layer image of the sample to be inspected and an average grayscale value of an image of the contrast enhancement layer is at least 50.

Abstract: A sample analyzing method and a sample preparing method are provided. The sample analyzing method includes a sample preparing step, a placing step, and an analyzing step. The sample preparing step includes an obtaining step implemented by obtaining an identification information; and a marking and placing step implemented by placing a sample carrying component having a sample disposed thereon into a marking equipment, allowing the marking equipment to utilize the identification information to form an identification structure on the sample carrying component, and placing the sample carrying component into one of the accommodating slots according to the identification information. The placing step is implemented by taking out the sample carrying component from one of the accommodating slots and placing the sample carrying component into an electron microscope equipment. The analyzing step is implemented by utilizing the electron microscope equipment to photograph the sample to generate an analyzation image.

Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.

Abstract: A mounting frame for being mounted with either one of first and second screwdrivers, includes a main frame, a mounting seat, and first and second mounting plates. The mounting seat has a plate attachment hole set. The first mounting plate has a first seat attachment hole set operable to be connected to the plate attachment hole set, and a first driver attachment hole set for the first screwdriver to be attached thereto. The second mounting plate has a second seat attachment hole set operable to be connected to the plate attachment hole set, and a second driver attachment hole set for the second screwdriver to be attached thereto.

Abstract: An electrode coupled double heterojunction solar cell having double active regions for photoelectric effect and method of manufacturing the same are provided. The electrode coupled double heterojunction solar cell includes a first terminal electrode, a first solar cell, a second solar cell, a common electrode structure, and a second terminal electrode. The first solar cell is connected to the first terminal electrode and includes a first PIN heterojunction structure. The second solar cell is disposed on the first solar cell and includes a second PIN heterojunction structure. The common electrode structure is disposed between the first solar cell and the second solar cell, so that the first solar cell and the second solar cell are electrically connected to each other in a parallel manner. The second terminal electrode is disposed on the second solar cell.

Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

Abstract: A cobalt electroplating composition may include (a) cobalt ions; and (b) an ammonium compound of formula (NR1R2R3H+)nXn?, wherein R1, R2, R3 are independently H or linear or branched C1 to C6 alkyl, X is one or more n valent inorganic or organic counter ion(s), and n is an integer from 1, 2, or 3.

Abstract: A fixing mechanism, applied to an electronic device to fix an electronic module. The fixing mechanism comprises a casing, a fixing structure and a locking structure. The casing includes a baseplate and a side plate to define a space to accommodate the electronic module, and the side plate has a hole and a seat. The fixing structure includes a fixing element and a pressing portion. The fixing element movably extends from the outer side of the side plate into the space through the hole. The pressing portion is rotatably disposed on the combining seat, and includes a first part having an opening and a second part corresponding to the fixing element. The locking structure is movably set in the opening, and includes an engaging element. When the engaging element is engaged in the opening, the locking structure presses against the side plate to fix the pressing portion.

Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

Abstract: A sample analyzing method and a sample preparing method are provided. The sample analyzing method includes a sample preparing step, a placing step, and an analyzing step. The sample preparing step includes an obtaining step implemented by obtaining an identification information; and a marking and placing step implemented by placing a sample carrying component having a sample disposed thereon into a marking equipment, allowing the marking equipment to utilize the identification information to form an identification structure on the sample carrying component, and placing the sample carrying component into one of the accommodating slots according to the identification information. The placing step is implemented by taking out the sample carrying component from one of the accommodating slots and placing the sample carrying component into an electron microscope equipment. The analyzing step is implemented by utilizing the electron microscope equipment to photograph the sample to generate an analyzation image.

Abstract: An equipment for manufacturing trampoline includes a rack, a rotation seat, a supporting platform, a plurality of fixing members, a driving member, a driving assembly, and at least one welding device. The rotation seat has a bearing rotatable with respect to the rack. The supporting platform is connected to the bearing. The fixing members are detachably disposed on the supporting platform. The driving member surrounds the supporting platform and is linked-up with the supporting platform. The driving assembly is connected to the driving member.

Abstract: A physical analysis method, a sample for physical analysis and a preparing method thereof are provided. The preparing method of the sample for physical analysis includes: providing a sample to be inspected; and forming a contrast enhancement layer on a surface of the sample to be inspected. The contrast enhancement layer includes a plurality of first material layers and a plurality of second material layers stacked upon one another. The first material layer and the second material layer are made of different materials. Each one of the first and second material layers has a thickness that does not exceed 0.1 nm. In an image captured by an electron microscope, a difference between an average grayscale value of a surface layer image of the sample to be inspected and an average grayscale value of an image of the contrast enhancement layer is at least 50.