Patents by Inventor Chieh Chu

Chieh Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220223373
    Abstract: A physical analysis method, a sample for physical analysis and a preparing method thereof are provided. The preparing method of the sample for physical analysis includes: providing a sample to be inspected; and forming a contrast enhancement layer on a surface of the sample to be inspected. The contrast enhancement layer includes a plurality of first material layers and a plurality of second material layers stacked upon one another. The first material layer and the second material layer are made of different materials. Each one of the first and second material layers has a thickness that does not exceed 0.1 nm. In an image captured by an electron microscope, a difference between an average grayscale value of a surface layer image of the sample to be inspected and an average grayscale value of an image of the contrast enhancement layer is at least 50.
    Type: Application
    Filed: December 23, 2021
    Publication date: July 14, 2022
    Inventors: CHIEN-WEI WU, KENG-CHIEH CHU, YUNG-SHENG FANG, CHUN-WEI WU, HUNG-JEN CHEN
  • Patent number: 11367300
    Abstract: A method for enabling an electronic device to receive a fingerprint data and an electronic device are disclosed. The electronic device includes a display unit and a sensing unit, and the display unit includes a green sub-pixel, a blue sub-pixel and a red sub-pixel. The method includes the following steps: the green sub-pixel of the display unit being in an on state, the blue sub-pixel and the red sub-pixel of the display unit being in off state; producing a visible light by the display unit; using the sensing unit to sense a reflected portion of the visible light; and receiving the fingerprint data from the sensing unit.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: June 21, 2022
    Assignee: InnoLux Corporation
    Inventors: I-Chieh Chu, Chuan-Chi Chien
  • Publication number: 20220108785
    Abstract: The present invention provides a medical image processing method, which comprises following steps of: receiving a three-dimensional model image file and at least one medical record data by a medical image processing device; creating a three-dimensional medical file based on the three-dimensional model image file and the at least one medical record data, wherein the three-dimensional medical file conforms to a digital imaging and communications in medicine standard; transmitting the three-dimensional medical file to a medical picture archiving and communication system; retrieving the three-dimensional medical file from the medical picture archiving and communication system by a three-dimensional medical image browsing device which is a non-workstation computer device loaded with a viewer software; and displaying the three-dimensional medical file.
    Type: Application
    Filed: July 13, 2021
    Publication date: April 7, 2022
    Inventors: Yen-Yu WANG, Chieh-Chu CHEN, Jing-Ying HUANG
  • Publication number: 20220030728
    Abstract: A fixing mechanism, applied to an electronic device to fix an electronic module. The fixing mechanism comprises a casing, a fixing structure and a locking structure. The casing includes a baseplate and a side plate to define a space to accommodate the electronic module, and the side plate has a hole and a seat. The fixing structure includes a fixing element and a pressing portion. The fixing element movably extends from the outer side of the side plate into the space through the hole. The pressing portion is rotatably disposed on the combining seat, and includes a first part having an opening and a second part corresponding to the fixing element. The locking structure is movably set in the opening, and includes an engaging element. When the engaging element is engaged in the opening, the locking structure presses against the side plate to fix the pressing portion.
    Type: Application
    Filed: July 2, 2021
    Publication date: January 27, 2022
    Inventors: Cheng-Wei CHEN, Kang-Yu LAI, Hsiu- Chieh CHU
  • Publication number: 20210299970
    Abstract: An equipment for manufacturing trampoline includes a rack, a rotation seat, a supporting platform, a plurality of fixing members, a driving member, a driving assembly, and at least one welding device. The rotation seat has a bearing rotatable with respect to the rack. The supporting platform is connected to the bearing. The fixing members are detachably disposed on the supporting platform. The driving member surrounds the supporting platform and is linked-up with the supporting platform. The driving assembly is connected to the driving member.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 30, 2021
    Inventor: Pin-Chieh CHU
  • Patent number: 11036901
    Abstract: The embodiments of the present disclosure provide a method and apparatus for simulating a flexible panel. The method comprises: establishing a geometric model of the flexible panel; cutting a layer adjacent to a layer where a wiring region is located in the geometric model of the flexible panel; partitioning the following regions or layers in the cut geometric model into grid cells: the wiring region, layers other than the layer where the wiring region located and the layer adjacent to the layer where the wiring region is located, and regions obtained by cutting the layer adjacent to the layer where the wiring region is located; and simulating the flexible panel based on the partition.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 15, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xixi Guo, Shang Chieh Chu, Shiming Shi
  • Publication number: 20210147994
    Abstract: A cobalt electroplating composition may include (a) cobalt ions; and (b) an ammonium compound of formula (NR1R2R3H+)nX1?, wherein R1, R2, R3 are independently H or linear or branched C1 to C6 alkyl, X is one or more n valent inorganic or organic counter ion(s), and n is an integer from 1, 2, or 3.
    Type: Application
    Filed: April 5, 2019
    Publication date: May 20, 2021
    Applicant: BASF SE
    Inventors: Marco ARNOLD, Chiao Chien WEI, Tzu Tsang HUANG, Shih Ming LIN, Cheng Chen KUO, Shih Wei CHOU, Chieh CHU
  • Publication number: 20210111182
    Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 15, 2021
    Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
  • Patent number: 10879257
    Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
  • Publication number: 20200265207
    Abstract: A method for enabling an electronic device to receive a fingerprint data and an electronic device are disclosed. The electronic device includes a display unit and a sensing unit, and the display unit includes a green sub-pixel, a blue sub-pixel and a red sub-pixel. The method includes the following steps: the green sub-pixel of the display unit being in an on state, the blue sub-pixel and the red sub-pixel of the display unit being in off state; producing a visible light by the display unit; using the sensing unit to sense a reflected portion of the visible light; and receiving the fingerprint data from the sensing unit.
    Type: Application
    Filed: February 3, 2020
    Publication date: August 20, 2020
    Inventors: I-Chieh Chu, Chuan-Chi Chien
  • Publication number: 20190163845
    Abstract: The embodiments of the present disclosure provide a method and apparatus for simulating a flexible panel. The method comprises: establishing a geometric model of the flexible panel; cutting a layer adjacent to a layer where a wiring region is located in the geometric model of the flexible panel; partitioning the following regions or layers in the cut geometric model into grid cells: the wiring region, layers other than the layer where the wiring region located and the layer adjacent to the layer where the wiring region is located, and regions obtained by cutting the layer adjacent to the layer where the wiring region is located; and simulating the flexible panel based on the partition.
    Type: Application
    Filed: May 22, 2018
    Publication date: May 30, 2019
    Inventors: Xixi Guo, Shang Chieh Chu, Shiming Shi
  • Patent number: 10269822
    Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
  • Publication number: 20190043878
    Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.
    Type: Application
    Filed: September 27, 2018
    Publication date: February 7, 2019
    Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
  • Patent number: 10091896
    Abstract: The present disclosure relates to the field of display devices and discloses a foldable display device comprising: a main body structure and a flexible screen provided on a surface of the main body structure; the main body structure includes two flat plate areas and a bending area connecting the two flat plates and making the two flat plate areas have an opening and closing angle of 0 degrees to at least 180 degrees between; the bending area having a minimum bending radius at the time of bending so that the flexible screen attached to the surface of the bending area also has a minimum bending radius, which is greater than a critical bending radius of the flexible screen. The present disclosure allows the flexible screen to have a minimum bending radius when the screen is folded, preventing the flexible screen from being damaged by excessive bending.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: October 2, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Shang Chieh Chu
  • Patent number: 9799755
    Abstract: A method for manufacturing a memory device includes forming trenches in a substrate to define an active region, filling an insulation material in the trenches, treating at least one portion of the insulation material, removing an upper portion of the insulation material from the trenches, so as to expose upper portions of side surfaces of the active region and to convert remaining portions of the insulation material in the trenches to shallow trench isolation (STI) disposed on opposite sides of the active region, forming a lower oxide layer, a middle charge trapping layer, and an upper oxide layer which cover the exposed upper portions of the side surfaces of the active region, an upper surface of the active region between the side surfaces of the active region, and the STI, and forming a gate layer on the upper oxide layer.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: October 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Yu Yang, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Jui-Yu Pan, Yun-Chi Wu, Yueh-Chieh Chu
  • Publication number: 20170303414
    Abstract: The present disclosure relates to the field of display devices and discloses a foldable display device comprising: a main body structure and a flexible screen provided on a surface of the main body structure; the main body structure includes two flat plat areas and a bending area connecting the two flat plates and making the two flat plate areas have an opening and closing angle of 0 degrees to at least 180 degrees between; the bending area having a minimum bending radius at the time of bending so that the flexible screen attached to the surface of the bending area also has a minimum bending radius, which is greater than a critical bending radius of the flexible screen. The present disclosure allows the flexible screen to have a minimum bending radius when the screen is folded, preventing the flexible screen from being damaged by excessive bending.
    Type: Application
    Filed: March 28, 2016
    Publication date: October 19, 2017
    Applicant: BOE TECHNOLOGY GROUP CO. LTD.
    Inventor: Shang Chieh CHU
  • Publication number: 20170278953
    Abstract: A method for manufacturing a memory device includes forming trenches in a substrate to define an active region, filling an insulation material in the trenches, treating at least one portion of the insulation material, removing an upper portion of the insulation material from the trenches, so as to expose upper portions of side surfaces of the active region and to convert remaining portions of the insulation material in the trenches to shallow trench isolation (STI) disposed on opposite sides of the active region, forming a lower oxide layer, a middle charge trapping layer, and an upper oxide layer which cover the exposed upper portions of the side surfaces of the active region, an upper surface of the active region between the side surfaces of the active region, and the STI, and forming a gate layer on the upper oxide layer.
    Type: Application
    Filed: September 14, 2016
    Publication date: September 28, 2017
    Inventors: Tsung-Yu YANG, Cheng-Bo SHU, Chung-Jen HUANG, Jing-Ru LIN, Jui-Yu PAN, Yun-Chi WU, Yueh-Chieh CHU
  • Publication number: 20170186762
    Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.
    Type: Application
    Filed: November 30, 2016
    Publication date: June 29, 2017
    Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
  • Patent number: 9642484
    Abstract: A dinnerware apparatus has an elongated solid storage tube having a through hole therein, a flexible cleaning brush retractably positioned in the through hole of the storage tube, and a connector affixed to an end of the brush holder. The flexible cleaning brush has an elongated flexible brush holder and a brushing portion affixed to an end of the brush holder. The connector has a service end and a mating end. The service end has a shape of a knife, fork, spoon, or a chopstick head. The mating end has a tight limiting section embedded at one end of the storage tube.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: May 9, 2017
    Inventors: Fu-Nan Chang, Hsueh-Chieh Chu
  • Patent number: 9620597
    Abstract: A graphene optoelectronic detector is disclosed, which comprises: an insulating substrate with a graphene layer disposed thereon; a first electrode disposed on the graphene layer or between the graphene layer and the insulating substrate; and a second electrode disposed on the graphene layer or between the graphene layer and the insulating substrate, wherein there is a predetermined distance between the first electrode and the second electrode, and the first electrode and the second electrode are at different electrical potentials, wherein a high-drift carrier moving region is disposed between the first electrode and the second electrode, and a low-drift carrier moving region is disposed outside the high-drift carrier moving region. In addition, the present invention further provides a method for detecting photons and electromagnetic energy using the aforementioned graphene detector.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 11, 2017
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Yon-Hua Tzeng, Chun-Cheng Chang, Pin-Yi Li, Yueh-Chieh Chu