Patents by Inventor Chieh Chu

Chieh Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210111182
    Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 15, 2021
    Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
  • Patent number: 10879257
    Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
  • Publication number: 20200265207
    Abstract: A method for enabling an electronic device to receive a fingerprint data and an electronic device are disclosed. The electronic device includes a display unit and a sensing unit, and the display unit includes a green sub-pixel, a blue sub-pixel and a red sub-pixel. The method includes the following steps: the green sub-pixel of the display unit being in an on state, the blue sub-pixel and the red sub-pixel of the display unit being in off state; producing a visible light by the display unit; using the sensing unit to sense a reflected portion of the visible light; and receiving the fingerprint data from the sensing unit.
    Type: Application
    Filed: February 3, 2020
    Publication date: August 20, 2020
    Inventors: I-Chieh Chu, Chuan-Chi Chien
  • Publication number: 20190163845
    Abstract: The embodiments of the present disclosure provide a method and apparatus for simulating a flexible panel. The method comprises: establishing a geometric model of the flexible panel; cutting a layer adjacent to a layer where a wiring region is located in the geometric model of the flexible panel; partitioning the following regions or layers in the cut geometric model into grid cells: the wiring region, layers other than the layer where the wiring region located and the layer adjacent to the layer where the wiring region is located, and regions obtained by cutting the layer adjacent to the layer where the wiring region is located; and simulating the flexible panel based on the partition.
    Type: Application
    Filed: May 22, 2018
    Publication date: May 30, 2019
    Inventors: Xixi Guo, Shang Chieh Chu, Shiming Shi
  • Patent number: 10269822
    Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
  • Publication number: 20190043878
    Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.
    Type: Application
    Filed: September 27, 2018
    Publication date: February 7, 2019
    Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
  • Patent number: 10091896
    Abstract: The present disclosure relates to the field of display devices and discloses a foldable display device comprising: a main body structure and a flexible screen provided on a surface of the main body structure; the main body structure includes two flat plate areas and a bending area connecting the two flat plates and making the two flat plate areas have an opening and closing angle of 0 degrees to at least 180 degrees between; the bending area having a minimum bending radius at the time of bending so that the flexible screen attached to the surface of the bending area also has a minimum bending radius, which is greater than a critical bending radius of the flexible screen. The present disclosure allows the flexible screen to have a minimum bending radius when the screen is folded, preventing the flexible screen from being damaged by excessive bending.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: October 2, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Shang Chieh Chu
  • Patent number: 9799755
    Abstract: A method for manufacturing a memory device includes forming trenches in a substrate to define an active region, filling an insulation material in the trenches, treating at least one portion of the insulation material, removing an upper portion of the insulation material from the trenches, so as to expose upper portions of side surfaces of the active region and to convert remaining portions of the insulation material in the trenches to shallow trench isolation (STI) disposed on opposite sides of the active region, forming a lower oxide layer, a middle charge trapping layer, and an upper oxide layer which cover the exposed upper portions of the side surfaces of the active region, an upper surface of the active region between the side surfaces of the active region, and the STI, and forming a gate layer on the upper oxide layer.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: October 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Yu Yang, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Jui-Yu Pan, Yun-Chi Wu, Yueh-Chieh Chu
  • Publication number: 20170303414
    Abstract: The present disclosure relates to the field of display devices and discloses a foldable display device comprising: a main body structure and a flexible screen provided on a surface of the main body structure; the main body structure includes two flat plat areas and a bending area connecting the two flat plates and making the two flat plate areas have an opening and closing angle of 0 degrees to at least 180 degrees between; the bending area having a minimum bending radius at the time of bending so that the flexible screen attached to the surface of the bending area also has a minimum bending radius, which is greater than a critical bending radius of the flexible screen. The present disclosure allows the flexible screen to have a minimum bending radius when the screen is folded, preventing the flexible screen from being damaged by excessive bending.
    Type: Application
    Filed: March 28, 2016
    Publication date: October 19, 2017
    Applicant: BOE TECHNOLOGY GROUP CO. LTD.
    Inventor: Shang Chieh CHU
  • Publication number: 20170278953
    Abstract: A method for manufacturing a memory device includes forming trenches in a substrate to define an active region, filling an insulation material in the trenches, treating at least one portion of the insulation material, removing an upper portion of the insulation material from the trenches, so as to expose upper portions of side surfaces of the active region and to convert remaining portions of the insulation material in the trenches to shallow trench isolation (STI) disposed on opposite sides of the active region, forming a lower oxide layer, a middle charge trapping layer, and an upper oxide layer which cover the exposed upper portions of the side surfaces of the active region, an upper surface of the active region between the side surfaces of the active region, and the STI, and forming a gate layer on the upper oxide layer.
    Type: Application
    Filed: September 14, 2016
    Publication date: September 28, 2017
    Inventors: Tsung-Yu YANG, Cheng-Bo SHU, Chung-Jen HUANG, Jing-Ru LIN, Jui-Yu PAN, Yun-Chi WU, Yueh-Chieh CHU
  • Publication number: 20170186762
    Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.
    Type: Application
    Filed: November 30, 2016
    Publication date: June 29, 2017
    Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
  • Patent number: 9642484
    Abstract: A dinnerware apparatus has an elongated solid storage tube having a through hole therein, a flexible cleaning brush retractably positioned in the through hole of the storage tube, and a connector affixed to an end of the brush holder. The flexible cleaning brush has an elongated flexible brush holder and a brushing portion affixed to an end of the brush holder. The connector has a service end and a mating end. The service end has a shape of a knife, fork, spoon, or a chopstick head. The mating end has a tight limiting section embedded at one end of the storage tube.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: May 9, 2017
    Inventors: Fu-Nan Chang, Hsueh-Chieh Chu
  • Patent number: 9620597
    Abstract: A graphene optoelectronic detector is disclosed, which comprises: an insulating substrate with a graphene layer disposed thereon; a first electrode disposed on the graphene layer or between the graphene layer and the insulating substrate; and a second electrode disposed on the graphene layer or between the graphene layer and the insulating substrate, wherein there is a predetermined distance between the first electrode and the second electrode, and the first electrode and the second electrode are at different electrical potentials, wherein a high-drift carrier moving region is disposed between the first electrode and the second electrode, and a low-drift carrier moving region is disposed outside the high-drift carrier moving region. In addition, the present invention further provides a method for detecting photons and electromagnetic energy using the aforementioned graphene detector.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 11, 2017
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Yon-Hua Tzeng, Chun-Cheng Chang, Pin-Yi Li, Yueh-Chieh Chu
  • Patent number: 9441191
    Abstract: A solid-state fermentation method is provided. The method is provided for edible and medicinal microorganisms. A commensurate device is used for processing sterilization, inoculation, cultivation, drying, and collection. Cultivation substrates are filled in cultivation plates and placed on trays of a movable layer rack in a reaction fermenter for fermentation. Inner pipes provide inoculation, fluid nutrient, and air for fermentation of microorganisms. The reaction fermenter is accompanied with a dry circulation unit and a production collection unit for drying and collection. The solid-state fermentation processes are thus effectively integrated without the need of transferring fermented products between stations, which largely reduces contamination rate. Even more, there is no need to purchase automatic production equipments of high mechanical technologies.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: September 13, 2016
    Assignee: TAIWAN LEADER BIOTECH CORP.
    Inventors: Chin-Chung Lin, Yu-Yen Lin, Jong-Tar Kuo, Chien-Chang Liao, Jent-turn Lee, Yu-Chieh Chu
  • Publication number: 20160190257
    Abstract: A graphene optoelectronic detector is disclosed, which comprises: an insulating substrate with a graphene layer disposed thereon; a first electrode disposed on the graphene layer or between the graphene layer and the insulating substrate; and a second electrode disposed on the graphene layer or between the graphene layer and the insulating substrate, wherein there is a predetermined distance between the first electrode and the second electrode, and the first electrode and the second electrode are at different electrical potentials, wherein a high-drift carrier moving region is disposed between the first electrode and the second electrode, and a low-drift carrier moving region is disposed outside the high-drift carrier moving region. In addition, the present invention further provides a method for detecting photons and electromagnetic energy using the aforementioned graphene detector.
    Type: Application
    Filed: June 26, 2015
    Publication date: June 30, 2016
    Inventors: YON-HUA TZENG, CHUN-CHENG CHANG, PIN-YI LI, YUEH-CHIEH CHU
  • Publication number: 20150353879
    Abstract: A solid-state fermentation method is provided. The method is provided for edible and medicinal microorganisms. A commensurate device is used for processing sterilization, inoculation, cultivation, drying, and collection. Cultivation substrates are filled in cultivation plates and placed on trays of a movable layer rack in a reaction fermenter for fermentation. Inner pipes provide inoculation, fluid nutrient, and air for fermentation of microorganisms. The reaction fermenter is accompanied with a dry circulation unit and a production collection unit for drying and collection. The solid-state fermentation processes are thus effectively integrated without the need of transferring fermented products between stations, which largely reduces contamination rate. Even more, there is no need to purchase automatic production equipments of high mechanical technologies.
    Type: Application
    Filed: June 5, 2014
    Publication date: December 10, 2015
    Inventors: Chin-Chung Lin, Yu-Yen Lin, Jong-Tar Kuo, Chien-Chang Liao, Jent-turn Lee, Yu-Chieh Chu
  • Patent number: 9106905
    Abstract: A layout method of sub-pixel renderings includes the following steps: providing an RGB pixel rendering, wherein each pixel of the RGB pixel rendering includes a plurality of sub-pixels, and the plurality of sub-pixels have different colors from each other; and when displaying a stereo image, dividing the RGB pixel rendering into a first sub-pixel rendering corresponding to a left-eye image and a second sub-pixel rendering corresponding to a right-eye image; wherein at least one of each row and each column of the first sub-pixel rendering includes R, G, and B sub-pixels, and at least one of each row and each column of the second sub-pixel rendering includes R, G, and B sub-pixels.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: August 11, 2015
    Assignee: AU Optronics Corp.
    Inventors: Hsueh-Yen Yang, Shang-Chieh Chu, Hong-Shen Lin
  • Publication number: 20150196150
    Abstract: A dinnerware with multifunctional configurations has a solid storage tube, designed into an extension tube made of stainless steel and a flexible cleaning brush set into the through hole of the solid storage tube in a retractable state. The flexible cleaning brush has a flexible long brush holder and a brushing portion mated at one end of said long brush holder. A dinnerware type connector is set at one end of the long brush holder opposite to the brushing portion. The service end contains either of a knife, fork, spoon or chopsticks head. The solid storage tube can be used separately as a common drinking pipette. When said solid cleaning brush is fully stretched into the through hole of the solid storage tube, the connector can be embedded into the end of said solid storage tube to form such dinnerware as knife, chopsticks, fork or soup spoon.
    Type: Application
    Filed: January 10, 2014
    Publication date: July 16, 2015
    Inventors: Fu-Nan CHANG, Hsueh-Chieh CHU
  • Publication number: 20150190004
    Abstract: A stainless steel beverage pipette, exclusively used for having a drink, has a solid body made of stainless steel. The external diameter of said solid body is 5 mm-15 mm. A through-hole is formed within the solid body. A top opening and a bottom opening with flat notch are set at both ends of said solid body. The inner and outer edges of said top and bottom openings are fitted with filleted corners, such that the cross sections of said top and bottom openings are of a semi-circular shape. The stainless steel beverage pipette is free of plasticizers ingredients, and is characterized by reusability, excellent durability and simple structure, and can thoroughly resolve the problems of the conventional plastic pipette, and improve the hygiene and food security with better applicability.
    Type: Application
    Filed: January 6, 2014
    Publication date: July 9, 2015
    Inventors: Fu-Nan CHANG, Hsueh-Chieh Chu
  • Publication number: 20150153876
    Abstract: The present invention relates to a touch display device, comprising: a display device; and a touch panel disposed on a side of the display device, wherein the touch panel comprises: a substrate; a shielding layer disposed between the substrate and the display device; and a wiring layer disposed between the shielding layer and the display device, comprising: a first signal electrode comprising a first overlap region and a first non-overlap region; and a second signal electrode comprising a second overlap region and a second non-overlap region; wherein the first overlap region and the second overlap region overlap with the shielding layer; and a spacing between the first overlap region and the second overlap region is greater than a spacing between the first non-overlap region and the second non-overlap region.
    Type: Application
    Filed: November 10, 2014
    Publication date: June 4, 2015
    Inventors: Charles CHIEN, I-Chieh CHU