Patents by Inventor Chieh Fang
Chieh Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990493Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, and a light-sensing region close to the front surface. The image sensor device includes an insulating layer covering the back surface and extending into the semiconductor substrate. The protection layer has a first refractive index, and the first refractive index is less than a second refractive index of the semiconductor substrate and greater than a third refractive index of the insulating layer, and the protection layer conformally and continuously covers the back surface and extends into the semiconductor substrate. The image sensor device includes a reflective structure surrounded by insulating layer in the semiconductor substrate.Type: GrantFiled: May 18, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Chieh Fang, Ming-Chi Wu, Ji-Heng Jiang, Chi-Yuan Wen, Chien-Nan Tu, Yu-Lung Yeh, Shih-Shiung Chen, Kun-Yu Lin
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Patent number: 11955312Abstract: A physical analysis method, a sample for physical analysis and a preparing method thereof are provided. The preparing method of the sample for physical analysis includes: providing a sample to be inspected; and forming a contrast enhancement layer on a surface of the sample to be inspected. The contrast enhancement layer includes a plurality of first material layers and a plurality of second material layers stacked upon one another. The first material layer and the second material layer are made of different materials. Each one of the first and second material layers has a thickness that does not exceed 0.1 nm. In an image captured by an electron microscope, a difference between an average grayscale value of a surface layer image of the sample to be inspected and an average grayscale value of an image of the contrast enhancement layer is at least 50.Type: GrantFiled: December 23, 2021Date of Patent: April 9, 2024Assignee: MATERIALS ANALYSIS TECHNOLOGY INC.Inventors: Chien-Wei Wu, Keng-Chieh Chu, Yung-Sheng Fang, Chun-Wei Wu, Hung-Jen Chen
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Publication number: 20240096712Abstract: Provided is a semiconductor device includes a gate electrode, a gate dielectric layer, a channel layer, an insulating layer, a first source/drain electrode and a second source/drain electrode, a second dielectric layer, and a stop segment. The gate electrode is located within a first dielectric layer that overlies a substrate. The gate dielectric layer is located over the gate electrode. The channel layer is located on the gate dielectric layer. The insulating layer is located over the channel layer. The first source/drain electrode and the second source/drain electrode are located in the insulating layer, and connected to the channel layer. The second dielectric layer is beside one of the first source/drain electrode and the second source/drain electrode. The stop segment is embedded in the second dielectric layer.Type: ApplicationFiled: January 10, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Wei Jiang, Chieh-Fang Chen, Yen-Chung Ho, Pin-Cheng Hsu, Feng-Cheng Yang, Chung-Te Lin
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Patent number: 11937426Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.Type: GrantFiled: May 3, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Ching Chu, Feng-Cheng Yang, Katherine H. Chiang, Chung-Te Lin, Chieh-Fang Chen
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Publication number: 20240064994Abstract: A memory device includes a plurality of first conductive pillars, a plurality of second conductive pillars, a plurality of gap filling pillars, a channel layer and first dielectric pillars. The gap filling pillars are located in between the first conductive pillars and the second conductive pillars. The channel layer is extending in a first direction, and located on side surfaces of the first conductive pillars and the second conductive pillars. The first dielectric pillars are located in between the channel layer and the plurality of gap filling pillars, wherein a length of an interface where the first dielectric pillars contact the gap filling pillars along the first direction is different from a length of the gap filling pillars along the first direction.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chieh-Fang Chen, Feng-Cheng Yang, Chung-Te Lin
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Publication number: 20230389320Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Feng-Ching Chu, Feng-Cheng Yang, Katherine H. Chiang, Chung-Te Lin, Chieh-Fang Chen
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Publication number: 20230167535Abstract: A fine metal mask includes a plate including a first and a second surfaces. The first surface has a first inner edge defining a first opening. The second surface has a second inner edge defining a second opening communicated with the first opening. The plate includes a first and a second curved surfaces respectively connecting the first surface inside the first opening and the second surface inside the second opening. The first and the second curved surfaces connect with a third inner edge defining a third opening smaller than the first and the second openings. The third inner edge includes a first straight edge, a second straight edge and a circular edge. The first and the second straight edges form an included angle. The circular edge has a radius smaller than or equal to 15 microns and connects between the first and the second straight edges.Type: ApplicationFiled: February 11, 2022Publication date: June 1, 2023Inventors: Kuan-Chieh FANG, Chi-Wei LIN
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Publication number: 20230024339Abstract: A method for forming a semiconductor memory structure is provided. The method includes forming a stack over a substrate, and the stack includes first dielectric layers and second dielectric layers vertically alternately arranged. The method also includes forming first dielectric pillars through the stack, and etching the stack to form first trenches. Sidewalls of the first dielectric pillars are exposed from the first trenches. The method also includes removing the first dielectric pillars to form through holes, removing the second dielectric layers of the stack to form gaps between the first dielectric layers, and forming first conductive lines in the gaps.Type: ApplicationFiled: February 9, 2022Publication date: January 26, 2023Inventors: Chih-Hsuan Cheng, Chieh-Fang Chen, Sheng-Chen Wang, Chieh-Yi Shen, Han-Jong Chia, Feng-Ching Chu, Meng-Han Lin, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
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Patent number: 11460945Abstract: An electronic device including a body, a controller, a first touch layer and a second touch layer is provided. The body includes a first operating region and a second operating region. The second operating region is divided into a first touch region, a second touch region and a third touch region located between the first touch region and the second touch region. The controller, the first touch layer and the second touch layer are disposed in the body, and the first touch layer and the second touch layer are electrically coupled to the controller. In a first mode, the controller controls the first touch layer to switch from a detection status to a working status. In a second mode, the controller controls the second touch layer to switch from the detection status to the working status. A control method of an electronic device is also provided.Type: GrantFiled: March 10, 2021Date of Patent: October 4, 2022Assignee: COMPAL ELECTRONICS, INC.Inventors: Hsin-Chieh Fang, Wang-Hung Yeh, Shu-Hung Lin
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Publication number: 20220278219Abstract: A method of manufacturing a diode structure includes forming a first stack on a silicon layer on a substrate. A first sidewall spacer extending along and covering a sidewall of the first stack is formed. The silicon layer is selectively etched to a first predetermined depth, thereby forming a second stack. The remaining silicon layer includes a silicon base. A second sidewall spacer extending along and covering a sidewall of the second stack is formed. The silicon base is selectively etched to form a third stack on the substrate. With the second sidewall spacer as a mask, lateral plasma ion implantation is performed. Defects at the interface between two adjacent semiconductor layers can be reduced by the method.Type: ApplicationFiled: May 11, 2022Publication date: September 1, 2022Inventors: Chieh-Fang CHEN, Kuo-Feng LO, Chung-Hon LAM, Yu ZHU
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Publication number: 20220278159Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, and a light-sensing region close to the front surface. The image sensor device includes an insulating layer covering the back surface and extending into the semiconductor substrate. The protection layer has a first refractive index, and the first refractive index is less than a second refractive index of the semiconductor substrate and greater than a third refractive index of the insulating layer, and the protection layer conformally and continuously covers the back surface and extends into the semiconductor substrate. The image sensor device includes a reflective structure surrounded by insulating layer in the semiconductor substrate.Type: ApplicationFiled: May 18, 2022Publication date: September 1, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Chieh FANG, Ming-Chi WU, Ji-Heng JIANG, Chi-Yuan WEN, Chien-Nan TU, Yu-Lung YEH, Shih-Shiung CHEN, Kun-Yu LIN
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Publication number: 20220238572Abstract: A method includes etching a semiconductor substrate to form a trench, filling a dielectric layer into the trench, with a void being formed in the trench and between opposite portions of the dielectric layer, etching the dielectric layer to reveal the void, forming a diffusion barrier layer on the dielectric layer, and forming a high-reflectivity metal layer on the diffusion barrier layer. The high-reflectivity metal layer has a portion extending into the trench. A remaining portion of the void is enclosed by the high-reflectivity metal layer.Type: ApplicationFiled: April 11, 2022Publication date: July 28, 2022Inventors: Ming-Chi Wu, Chun-Chieh Fang, Bo-Chang Su, Chien Nan Tu, Yu-Lung Yeh, Kun-Yu Lin, Shih-Shiung Chen
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Publication number: 20220223618Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.Type: ApplicationFiled: May 3, 2021Publication date: July 14, 2022Inventors: Feng-Ching Chu, Feng-Cheng Yang, Katherine H. Chiang, Chung-Te Lin, Chieh-Fang Chen
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Publication number: 20220199459Abstract: An LDMOS device comprises a well region, first and second implant regions, a gate electrode, first and second source/drain regions, a first STI region, and a first DTI region. The well region is in a substrate and of a first conductivity type. The first implant region is in the substrate and of a second conductivity type. The second implant region is in the well region and of the first conductivity type. The gate electrode extends from above the well region to above the first implant region. The first and second source/drain regions are respectively in the first and second implant regions. The first STI region laterally extends from the second implant region to directly below the gate electrode. The first DTI region extends downwards from a bottom surface of the first STI region into the well region. The first DTI region vertically overlaps with the gate electrode.Type: ApplicationFiled: March 14, 2022Publication date: June 23, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Chieh FANG, Chien-Chang HUANG, Chi-Yuan WEN, Jian WU, Ming-Chi WU, Jung-Yu CHENG, Shih-Shiung CHEN, Wei-Tung HUANG, Yu-Lung YEH
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Patent number: 11362192Abstract: A method of manufacturing a diode structure includes forming a first stack on a silicon layer on a substrate. A first sidewall spacer extending along and covering a sidewall of the first stack is formed. The silicon layer is selectively etched to a first predetermined depth, thereby forming a second stack. The remaining silicon layer includes a silicon base. A second sidewall spacer extending along and covering a sidewall of the second stack is formed. The silicon base is selectively etched to form a third stack on the substrate. With the second sidewall spacer as a mask, lateral plasma ion implantation is performed. Defects at the interface between two adjacent semiconductor layers can be reduced by the method.Type: GrantFiled: August 13, 2020Date of Patent: June 14, 2022Assignees: JIANGSU ADVANCED MEMORY TECHNOLOGY CO., LTD., JIANGSU ADVANCED MEMORY SEMICONDUCTOR CO., LTD.Inventors: Chieh-Fang Chen, Kuo-Feng Lo, Chung-Hon Lam, Yu Zhu
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Patent number: 11342372Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a first side, a second side opposite to the first side, and at least one light-sensing region close to the first side. The image sensor device includes a dielectric feature covering the second side and extending into the semiconductor substrate. The dielectric feature in the semiconductor substrate surrounds the light-sensing region. The image sensor device includes a reflective layer in the dielectric feature in the semiconductor substrate, wherein a top portion of the reflective layer protrudes away from the second side, and a top surface of the reflective layer and a top surface of the insulating layer are substantially coplanar.Type: GrantFiled: July 9, 2020Date of Patent: May 24, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Chieh Fang, Ming-Chi Wu, Ji-Heng Jiang, Chi-Yuan Wen, Chien-Nan Tu, Yu-Lung Yeh, Shih-Shiung Chen, Kun-Yu Lin
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Patent number: 11302734Abstract: A method includes etching a semiconductor substrate to form a trench, filling a dielectric layer into the trench, with a void being formed in the trench and between opposite portions of the dielectric layer, etching the dielectric layer to reveal the void, forming a diffusion barrier layer on the dielectric layer, and forming a high-reflectivity metal layer on the diffusion barrier layer. The high-reflectivity metal layer has a portion extending into the trench. A remaining portion of the void is enclosed by the high-reflectivity metal layer.Type: GrantFiled: September 4, 2018Date of Patent: April 12, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chi Wu, Chun-Chieh Fang, Bo-Chang Su, Chien Nan Tu, Yu-Lung Yeh, Kun-Yu Lin, Shih-Shiung Chen
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Patent number: D976894Type: GrantFiled: September 18, 2019Date of Patent: January 31, 2023Assignee: COMPAL ELECTRONICS, INC.Inventors: Jen-Yu Chiang, Wang-Hung Yeh, Hsin-Chieh Fang, Shu-Hsien Chu
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Patent number: D1010638Type: GrantFiled: February 18, 2020Date of Patent: January 9, 2024Assignee: Compal Electronics, Inc.Inventors: Jen-Yu Chiang, Wang-Hung Yeh, Hsin-Chieh Fang, Shu-Hsien Chu, Jia-Sheng Chen
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Patent number: D1026916Type: GrantFiled: January 5, 2022Date of Patent: May 14, 2024Assignee: COMPAL ELECTRONICS, INC.Inventors: Hao-Jen Fang, Kung-Ju Chen, Wei-Yi Chang, Chun-Chieh Chen, Chih-Wen Chiang, Sheng-Hung Lee