Patents by Inventor Chieh Fang

Chieh Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170141767
    Abstract: A buffer circuit includes a transistor cascode circuit, a latch circuit, a first transistor, a second transistor, and a voltage generator. The transistor cascode circuit is biasing at a first voltage. The latch circuit is biasing at a second voltage, whose voltage level is negative. The first transistor and the second transistor are coupling between the transistor cascode circuit and the latch circuit, and a gate of the first transistor is coupled to a gate of the second transistor. The voltage generator provides a biasing voltage to the gate of the first transistor and adjusts a voltage level of the biasing voltage dynamically according to a voltage level of the second voltage. The biasing voltage is at a first level when the buffer circuit is initially turned on, and the biasing voltage is at a second level when the buffer circuit enters the steady state.
    Type: Application
    Filed: October 6, 2016
    Publication date: May 18, 2017
    Applicant: ALi Corporation
    Inventors: Wei-Chieh FANG, Chien-Yuan LU
  • Publication number: 20160372360
    Abstract: A semiconductor structure is provided, which includes a semiconductor substrate, a first well region, a second well region, an active region, a shallow trench isolation (STI) and at least one deep trench isolation (DTI). The first well region of a first conductive type is on the semiconductor substrate. The second well region of a second conductive type is on the semiconductor substrate and adjacent to the first well region. The second conductive type is different from the first conductive type. The active region is on the first well region. The active region has a conductive type the same as the second conductive type of the second well region. The STI is between the first and second well regions. The DTI is below the STI. The DTI is disposed between at least a portion of the first well region and at least a portion of the second well region.
    Type: Application
    Filed: June 17, 2015
    Publication date: December 22, 2016
    Inventors: Chun-Chieh FANG, Chien-Chang HUANG, Chi-Yuan WEN, Jian WU, Ming-Chi WU, Jung-Yu CHENG, Shih-Shiung CHEN, Wei-Tung HUANG, Yu-Lung YEH
  • Publication number: 20160349909
    Abstract: A portable electronic device includes a first body and a second body. The second body includes a processing unit, and a first touch panel, a second touch panel, a keyboard and at least one detecting module electrically connected to the processing unit, respectively. The keyboard is slidably disposed above the second touch panel, and the detecting module is adapted to detect a position of the keyboard. When the keyboard is located at a first position, the keyboard module covers the second touch panel, and the detecting module transmits a first signal to the processing unit so that the first touch panel is turned on. When the keyboard is located at a second position, the keyboard exposes the second touch panel, and the detecting module transmits a second signal to the processing unit so that the first touch panel is turned off. A touch panel controlling method of the portable electronic device is further provided.
    Type: Application
    Filed: June 1, 2016
    Publication date: December 1, 2016
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Ming-Shun Lu, Ming-Chung Liu, Hsin-Chieh Fang, Yu-Wen Cheng, Yu-Ning Chang
  • Publication number: 20160307946
    Abstract: A semiconductor device includes a carrier, a substrate, light-sensing devices and a bonding layer. The substrate overlies the carrier, and has a first surface and a second surface opposite to the first surface. The substrate includes inverted pyramid recesses in the second surface. The light-sensing devices are disposed on the first surface of the substrate. The bonding layer is disposed between the substrate and the carrier.
    Type: Application
    Filed: April 16, 2015
    Publication date: October 20, 2016
    Inventors: Chien-Chang HUANG, Wei-Tung HUANG, Yen-Hsiang HSU, Yu-Lung YEH, Chun-Chieh FANG
  • Publication number: 20160155476
    Abstract: An event data recorder with a communication module and a method thereof are applicable to a vehicle. The event data recorder comprises: a communication module, electrically connected to a receiving and transmitting antenna unit, for receiving and transmitting a communication signal and establishing a network connection for the communication signal; a lens, for acquiring an image record when the vehicle travels; a micro-control unit, for storing the image record into a memory unit and uploading the image record into a storage server through the network connection; and a global satellite positioning module, for acquiring position information of the vehicle, storing the position information into the memory unit, and uploading the position information into the storage server through the network connection.
    Type: Application
    Filed: March 23, 2015
    Publication date: June 2, 2016
    Inventor: Chih-Chieh FANG
  • Publication number: 20160134808
    Abstract: A 360-degree panorama driving recorder system for use in a carrier, including a display unit for displaying image records, three lens and three sensors respectively electrically connected together and mounted inside the carrier for capturing different view angle image records, and a microcontroller unit electrically coupled with the sensors for receiving and integrating the view angle image records captured through the lenses during running of the carrier into an integrated 360-degree panorama image record and then transmitting the integrated panorama image record to the display unit for display.
    Type: Application
    Filed: March 23, 2015
    Publication date: May 12, 2016
    Inventor: Chih-Chieh FANG
  • Patent number: 9330764
    Abstract: A device, such as an integrated circuit including memory, includes an array of memory cells on a substrate. A row/column line, such as a local word line or local bit line, is disposed in the array. The row/column line includes a pass transistor structure comprising a semiconductor strip in a first patterned layer over the substrate. The semiconductor strip includes a semiconductor channel body, a contact region on one side of the semiconductor channel body, and an extension on another side of the semiconductor channel body, which reaches into the memory cells in the array. A select line in a second patterned layer crossing the semiconductor channel body is provided. The pass transistor structure can be implemented in a fanout structure for row/column lines in the array.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: May 3, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Lee-Yin Lin, Teng-Hao Yeh, Chih-Wei Hu, Chieh-Fang Chen
  • Publication number: 20150364196
    Abstract: A device, such as an integrated circuit including memory, includes an array of memory cells on a substrate. A row/column line, such as a local word line or local bit line, is disposed in the array. The row/column line includes a pass transistor structure comprising a semiconductor strip in a first patterned layer over the substrate. The semiconductor strip includes a semiconductor channel body, a contact region on one side of the semiconductor channel body, and an extension on another side of the semiconductor channel body, which reaches into the memory cells in the array. A select line in a second patterned layer crossing the semiconductor channel body is provided. The pass transistor structure can be implemented in a fanout structure for row/column lines in the array.
    Type: Application
    Filed: June 16, 2014
    Publication date: December 17, 2015
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: LEE-YIN LIN, TENG-HAO YEH, CHIH-WEI HU, CHIEH-FANG CHEN
  • Patent number: 8779408
    Abstract: A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: July 15, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Ming-Hsiu Lee, Chieh-Fang Chen
  • Patent number: 8772747
    Abstract: A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: July 8, 2014
    Assignees: Macronix International Co., Ltd., International Business Machines Corporation
    Inventors: Huai-Yu Cheng, Chieh-Fang Chen, Hsiang-Lan Lung, Yen-Hao Shih, Simone Raoux, Matthew J. Breitwisch
  • Patent number: 8678031
    Abstract: A nuclear plant is provided with a pipe-passivating alkali-injecting device including an alkali-injecting tank, an actuator, a counter-balance valve, a pressure gauge, exhaust valves and switching valves. The actuator is connected to the alkali-injecting tank via a first pipe. The counter-balance valve is connected to the actuator via a second pipe and connected to the alkali-injecting tank via a third pipe. The pressure gauge is provided between the actuator and the counter-balance valve and connected to the second pipe. The exhaust valves are connected to the first and second pipes, and so are the switching valves. The alkali-injecting tank, the actuator and the counter-balance valve are used together to expel gases from the pipes while injecting alkali, thus effectively avoiding feedback of liquid in the nuclear plant, transmitting pure alkali in the pipes, and reducing damage to the pipes.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: March 25, 2014
    Assignee: Institute of Nuclear Energy Research, Atomic Energy Council
    Inventors: Ning-Yih Hsu, Chieh Fang, Hwa-Yuan Tzeng, Chen-To Tsai, Tung-Jen Wen
  • Patent number: 8623734
    Abstract: An example embodiment is a method for filling a via hole with phase change material. The method steps include forming a bottom electrode in a substrate, depositing a dielectric layer above the bottom electrode, and forming a via hole within the dielectric layer down to a top surface of the bottom electrode. The substrate is heated to a reaction temperature and a first phase change material precursor is deposited within the via hole. The first precursor is configured to decompose on the top surface of the bottom electrode and chemisorb on a top surface of the dielectric layer at the reaction temperature. A second precursor is deposited within the via hole after the first precursor at least partially decomposes on the top surface of the bottom electrode.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chieh-Fang Chen, Chung H. Lam, Alejandro G. Schrott
  • Patent number: 8564524
    Abstract: A flat panel display comprises a display panel, a scan driving circuit and a control unit, wherein the display panel includes a plurality of scan lines. The scan driving circuit generates the first and the second scan signals to enable a portion of the scan lines. Furthermore, the control unit may enable a control signal every a predetermined duration according to these scan lines.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: October 22, 2013
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Chang-Ching Tu, Yu-Chieh Fang
  • Patent number: 8537609
    Abstract: A memory device is provided. The memory device includes a memory array; a first circuit electrically connected to the memory array, and causing the memory array to be operated in a first mode; and a second circuit electrically connected to the memory array, and causing the memory array to be operated in a second mode.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: September 17, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Ming-Hsiu Lee, Chieh-Fang Chen
  • Publication number: 20130234093
    Abstract: A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition.
    Type: Application
    Filed: April 22, 2013
    Publication date: September 12, 2013
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, MACRONIX INTERNATIONAL CO., LTD.
    Inventors: HUAI-YU CHENG, CHIEH-FANG CHEN, HSIANG-LAN LUNG, YEN-HAO SHIH, SIMONE RAOUX, MATTHEW J. BREITWISCH
  • Publication number: 20130183801
    Abstract: A method for manufacturing semiconductor devices includes providing a substrate having a first region and a second region defined thereon, and a shallow trench isolation (STI) formed in between the first region and the second region, the first region comprising a first gate structure and the second region comprising a second gate structure respectively formed therein; forming a patterned protecting layer covering at least the entire STI and the second region on the substrate; forming recesses not exposing the STI in the substrate respectively at two sides of the first gate structure; and forming an epitaxial layer in the recesses respectively, the epitaxial layer filling up the recesses.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 18, 2013
    Inventors: Tsung-Min Kuo, Feng-Mou Chen, Wei-Che Chen, Chun-Chieh Fang
  • Patent number: 8456539
    Abstract: A method of automatic task execution is adapted to be performed by an electronic apparatus that includes an image-capturing module and a processing module. The method includes the steps of: a) recording in the processing module a relationship between a visible physical attribute of an object and a corresponding task to be executed by the processing module; b) configuring the electronic apparatus for capturing an image containing a target using the image-capturing module; c) configuring the processing module to determine if the visible physical attribute of the object is found in the image captured by the image-capturing module; and d) when the visible physical attribute of the object is found in the image, configuring the processing module to execute the corresponding task automatically.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: June 4, 2013
    Assignee: National Taiwan University
    Inventors: Hsien-Hui Tang, Wen-Jong Wu, Yueh-Hsien Lin, Chih-Ying Yang, Yang-Bee Lee, Wen-Chieh Fang, Mu-Chern Fong, Cheng-Wei Chen, Gwen Hsiao
  • Patent number: 8455443
    Abstract: A wound healing composition comprising a class of polypeptide compounds having a polypeptide chain with 5 to 120 amino acid units per chain. The composition includes a pharmaceutical medium to carry the polypeptide compound, such as an aqueous solution, suspension, dispersion, salve, ointment, gel, cream, lotion, spray or paste. Additionally, a method of applying a wound healing composition comprising a class of polypeptide compounds having a polypeptide chain with 5 to 120 amino acid units per chain in a concentration of from about 1 ?g/ml to about 100 ?g/ml for a time sufficient to heal the wound is disclosed.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: June 4, 2013
    Assignee: University of Southern California
    Inventors: Wei Li, Mei Chen, David T. Woodley, Chieh-Fang Cheng
  • Patent number: 8445313
    Abstract: A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: May 21, 2013
    Assignees: International Business Machines Corporatoin, Macronix International Co., Ltd.
    Inventors: Matthew J. Breitwisch, Chieh-Fang Chen, Shih-Hung Chen, Eric A. Joseph, Chung Hon Lam, Michael F. Lofaro, Hsiang-Lan Lung, Alejandro G. Schrott, Min Yang
  • Patent number: 8426242
    Abstract: A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: April 23, 2013
    Assignees: Macronix International Co., Ltd., International Business Machines Corporation
    Inventors: Huai-Yu Cheng, Chieh-Fang Chen, Hsiang-Lan Lung, Yen-Hao Shih, Simone Raoux, Matthew J. Breitwisch