Chien Chih Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A polyester film and a method for producing the same are provided. The polyester film includes a heat resistant layer. The heat resistant layer includes a high temperature resistant resin material and a polyester resin material. The high temperature resistant resin material and the polyester resin material are melted and kneaded with each other via a twin screw granulator. The twin-screw granulator has a twin-screw temperature between 250° C. and 320° C., and the twin-screw granulator has a twin-screw rotation speed between 300 rpm and 800 rpm, so that the high temperature resistant resin material is dispersed in the polyester resin material with a particle size of between 50 nm and 200 nm.
April 3, 2020
February 25, 2021
Wen-Cheng Yang, TE-CHAO LIAO, HAO-SHENG CHEN, Chien-Chih Lin
Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.
May 8, 2020
Date of Patent:
February 23, 2021
Taiwan Semiconductor Manufacturing Company Ltd.
Abstract: A method according to the present disclosure includes providing a substrate, depositing an underlayer over the substrate, depositing a photoresist layer over the underlayer, exposing a portion of the photoresist layer and a portion of the underlayer to a radiation source according to a pattern, baking the photoresist layer and underlayer, and developing the exposed portion of the photoresist layer to transfer the pattern to the photoresist layer. The underlayer includes a polymer backbone, a polarity switchable group, a cross-linkable group bonded to the polymer backbone, and photoacid generator. The polarity switchable group includes a first end group bonded to the polymer backbone, a second end group including fluorine, and an acid labile group bonded between the first end group and the second end group. The exposing decomposes the photoacid generator to generate an acidity moiety that detaches the second end group from the polymer backbone during the baking.
Abstract: In an embodiment, a workstation includes: a processing chamber configured to process a workpiece; a load port configured to interface with an environment external to the workstation; a robotic arm configured to transfer the workpiece between the load port and the processing chamber; and a defect sensor configured to detect a defect along a surface of the workpiece when transferred between the load port and the processing chamber.
Abstract: A lithography method includes forming a bottom anti-reflective coating (BARC) layer on a substrate, wherein the BARC layer includes an organic polymer and a reactive chemical group having at least one of chelating ligands and capping monomers, wherein the reactive chemical group is bonded to the organic polymer; coating a metal-containing photoresist (MePR) layer on the BARC layer, wherein the MePR being sensitive to an extreme ultraviolet (EUV) radiation; performing a first baking process to the MePR layer and the BARC layer, thereby reacting a metal chemical structure of the MePR layer and the reactive chemical structure of the BARC layer and forming an interface layer between the MePR layer and the BARC layer; performing an exposure process using the EUV radiation to the MePR layer; and developing the MePR layer to form a patterned photoresist layer.
Abstract: A support mechanism includes a fixed body, a rotating unit, a moving unit and a driving unit. The rotating unit is rotationally mounted to the fixed body. The moving unit, disposed at the fixed body, includes a ball screw spline shaft, a ball screw nut and a ball spline nut. The ball screw nut and the ball spline nut are both rotatably disposed at the ball screw spline shaft moved together with the rotating unit. The driving unit, disposed at the fixed body, includes a first driving member and a second driving member to rotate the ball screw nut and the ball spline nut, respectively. With different rotation pairs of the ball screw nut and the ball spline nut to the ball screw spline shaft, the ball screw spline shaft is driven to move, and the ball screw spline shaft is further to move the rotating unit.
Abstract: The present invention provides an antenna structure, an antenna device and a wireless localization method. The antenna structure includes a first radiation unit including a plurality of first connecting portions and a plurality of first annular radiation portions, a second radiation unit including a plurality of second connecting portions and a plurality of second annular radiation portions, a first conductive wire and a plurality of second conductive wires. A first end of each first annular radiation portion is connected to the first connecting portion, and the second end thereof extends towards the first end of the adjacent first annular radiation portion. A first end of each second annular radiation portion is connected to the second connecting portion, and the second end thereof extends towards the first end of the adjacent second annular radiation portion.
Abstract: A separate quantization method of forming a combination of 4-bit and 8-bit data of a neural network is disclosed. When a training data set and a validation data set exist, a calibration manner is used to determine a threshold for activations of each of a plurality of layers of a neural network model, so as to determine how many of the activations to perform 8-bit quantization. In a process of weight quantization, the weights of each layer are allocated to 4-bit weights and 8-bit weights according to a predetermined ratio, so as to make the neural network model have a reduced size and a combination of 4-bit and 8-bit weights.
Abstract: A connector assembly is provided which includes a shielding shell, a receptacle connector and a heat sink. The shielding shell has a top wall, a receiving cavity positioned inside, an inserting opening which is positioned at a front end of the shielding shell and communicated with the receiving cavity and a window which is formed to the top wall, extends rearwardly and is communicated with the receiving cavity. The receptacle connector is provided to a rear segment of the receiving cavity. The heat sink is provided to the top wall and includes a heat dissipating base. A bottom face of the heat dissipating base downwardly enters the receiving cavity via the window and directly faces a top face of the receptacle connector. The bottom face of the heat dissipating base facing the receptacle connector is provided with a front stopping portion which is adapted to stop a mating module.
Abstract: A semiconductor device includes: a metal thin film disposed on a semiconductor substrate; and first and second contact structures disposed on the metal thin film, wherein the first and second contact structures are laterally spaced from each other by a dummy layer that comprises at least one polishing resistance material.
Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage region and a high voltage region are integrated in a substrate. A low voltage transistor device is disposed in the low voltage region and comprises a low voltage gate electrode and a low voltage gate dielectric separating the low voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage gate electrode and the low voltage gate dielectric. A high voltage transistor device is disposed in the high voltage region and comprises a high voltage gate electrode disposed on the first interlayer dielectric layer.
Abstract: A barcode detection method includes obtaining a gradient of each pixel in an image, generating a gradient phase and a gradient magnitude of each pixel according to the gradient, and binarizing the gradient magnitude of each pixel to generate a binary image, generating a sliding window on the image, sampling the binary image vertically and horizontally within the sliding window to generate the numbers of grayscale value variations in the vertical and horizontal directions, locating the most intensive flip region according to the grayscale variations in the vertical and horizontal directions, locating a core barcode region according to the most intensive flip region, capturing the gradient phase of the pixels in the core barcode region to generate a gradient phase distribution, generating a barcode format detection result according to the gradient phase distribution, and locating the barcode region according to the barcode format detection result.
Abstract: A method is provided and includes the following steps. A first wafer is coupled to a first support of a bonding tool and a second wafer is coupled to a second support of the bonding tool. The second wafer is bonded to the first wafer with the first wafer coupled to the first support. Whether a bubble is between the bonded first and second wafers in the bonding tool is detected.
Abstract: The invention relates to an electrochemical dephosphorylation technique for treating Alzheimer's disease and a use thereof. It comprises a gold electrode provided with a negative potential of ?0.2 V to ?0.6 V on a surface thereof.
Abstract: A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.
Abstract: In an embodiment, a system includes: a cassette comprising a slit opening configured to house a wafer; a blade configured to move the wafer to and from the slit opening by extending into the slit opening, wherein a blade thickness of the blade is at most ? of a height of the slit opening and wherein the blade is configured to secure the wafer within a pocket on the blade that is at least ? of a wafer thickness of the wafer.
June 22, 2020
December 10, 2020
Chien-Chih Chen, Yao-Min Yu, Ching-Ling Lee, Ren-Dou Lee
Abstract: An optical apparatus that includes: a semiconductor substrate formed from a first material, the semiconductor substrate including a first n-doped region; and a photodiode supported by the semiconductor substrate, the photodiode including an absorption region configured to absorb photons and to generate photo-carriers from the absorbed photons, the absorption region being formed from a second material different than the first material and including: a first p-doped region; and a second n-doped region coupled to the first n-doped region, wherein a second doping concentration of the second n-doped region is less than or substantially equal to a first doping concentration of the first n-doped region.
Abstract: A contra-rotating fan structure includes a first base, a first fan, a second base, and a second fan. The first fan is rotatably disposed on the first base and includes a first hub. The first hub has a first largest width. The second fan is rotatably disposed on the second base and includes a second hub. The second hub has a second largest width. The first base and the second base are located between the first fan and the second fan. The second largest width is greater than the first largest width.
Abstract: Some embodiments relate to an integrated circuit (IC) that includes a semiconductor substrate. A shallow trench isolation region downwardly extends into the frontside of the semiconductor substrate and is filled with dielectric material. A first capacitor plate and a second capacitor plate are disposed in the shallow trench isolation region. The first capacitor plate and the second capacitor plate have first and second sidewall structures, respectively, that are substantially parallel to one another and that are separated from one another by the dielectric material of the shallow trench isolation region.
September 23, 2019
December 3, 2020
Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Kong-Beng Thei
Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.