Patents by Inventor Chien Chih Chen

Chien Chih Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11782345
    Abstract: A method according to the present disclosure includes providing a substrate, depositing an underlayer over the substrate, depositing a photoresist layer over the underlayer, exposing a portion of the photoresist layer and a portion of the underlayer to a radiation source according to a pattern, baking the photoresist layer and underlayer, and developing the exposed portion of the photoresist layer to transfer the pattern to the photoresist layer. The underlayer includes a polymer backbone, a polarity switchable group, a cross-linkable group bonded to the polymer backbone, and photoacid generator. The polarity switchable group includes a first end group bonded to the polymer backbone, a second end group including fluorine, and an acid labile group bonded between the first end group and the second end group. The exposing decomposes the photoacid generator to generate an acidity moiety that detaches the second end group from the polymer backbone during the baking.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Chih Chen, Ching-Yu Chang
  • Publication number: 20230273524
    Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.
    Type: Application
    Filed: December 12, 2022
    Publication date: August 31, 2023
    Inventors: Shih-Ming Chang, Wen Lo, Chun-Hung Liu, Chia-Hua Chang, Hsin-Wei Wu, Ta-Wei Ou, Chien-Chih Chen, Chien-Cheng Chen
  • Publication number: 20230261009
    Abstract: An electronic device having a peripheral area and a non-peripheral area adjacent to the peripheral area is provided. The electronic device includes a flexible substrate, a first conductive layer disposed on the flexible substrate and disposed in the peripheral area and the non-peripheral area, an organic layer disposed in the non-peripheral area and on the first conductive layer, a second conductive layer disposed on the first conductive layer, and an organic structure disposed between the first conductive layer and the second conductive layer in the peripheral area. The organic layer and the organic structure are the same material layer.
    Type: Application
    Filed: April 21, 2023
    Publication date: August 17, 2023
    Inventors: Ti-Chung CHANG, Chih-Chieh WANG, Chien-Chih CHEN
  • Patent number: 11688620
    Abstract: In an embodiment, a system includes: a cassette comprising a slit opening configured to house a wafer; a blade configured to move the wafer to and from the slit opening by extending into the slit opening, wherein a blade thickness of the blade is at most ? of a height of the slit opening and wherein the blade is configured to secure the wafer within a pocket on the blade that is at least ? of a wafer thickness of the wafer.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Chih Chen, Yao-Min Yu, Ching-Ling Lee, Ren-Dou Lee
  • Patent number: 11664390
    Abstract: An electronic device is provided. The electronic device includes a supporting substrate, a flexible substrate disposed on the supporting substrate, a first conductive layer disposed on the flexible substrate, a second conductive layer disposed on the first conductive layer, a plurality of organic elements disposed between the first conductive layer and the second conductive layer, and an opening passing through the supporting substrate and exposing a portion of the flexible substrate. The first conductive layer alternately contacts the second conductive layer and the plurality of organic elements.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: May 30, 2023
    Assignee: INNOLUX CORPORATION
    Inventors: Ti-Chung Chang, Chih-Chieh Wang, Chien-Chih Chen
  • Patent number: 11656299
    Abstract: A near magnetic field variation detection method comprises following steps of: measuring magnetic field by a first magnetic field sensor and a second magnetic field sensor respectively; and calculating a magnetic field measurement difference, wherein the magnetic field measurement difference is (1) a magnitude of a difference of a first-magnetic-field-measurement measured by the first magnetic field sensor and a second-magnetic-field-measurement measured by the second magnetic field sensor, or (2) a magnitude of a difference of a first-magnetic-field-measurement-component measured by the first magnetic field sensor along a characteristic direction and a second-magnetic-field-measurement-component measured by the second magnetic field sensor along the characteristic direction; wherein a near magnetic field variation is occurred when (a) the magnetic field measurement difference is continuously greater than a characteristic-threshold within a characteristic-time-period, or (b) an average value of the magnetic f
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: May 23, 2023
    Assignee: NATIONAL CENTRAL UNIVERSITY
    Inventor: Chien-Chih Chen
  • Patent number: 11648233
    Abstract: The present invention is related to an active substance of Hericium erinaceus having a pain-relieving effect, and a pharmaceutical composition including the active substance. The active substance is prepared using the following steps: (a) inoculating a mycelium of H. erinaceus on an agar plate and incubating at 15-32° C. for 8-16 days; (b) inoculating the incubated H. erinaceus mycelia from step (a) into a medium in a flask and incubating at 20-30° C. and pH 4.5-6.5 for 3-5 days; (c) inoculating the incubated H. erinaceus mycelia from step (b) into a medium in a fermentation tank and incubating at 24-32° C. and pH 4.5-5.5 for 8-16 days to obtain a fermented medium of the H. erinaceus mycelia; and (d) desiccating the fermented medium of the H. erinaceus mycelia from step (c) to obtain the powder of the H. erinaceus mycelia, which is further purified and isolated to obtain a novel compound of H. erinaceus.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: May 16, 2023
    Assignee: GRAPE KING BIO LTD.
    Inventors: Pei-Shan Liu, Chien-Chih Chen, Chin-Chu Chen, Li-Ya Lee, Wan-Ping Chen, Ting-Wei Lin, Jui-Hsia Hsu, Wei-Ching Chu
  • Patent number: 11651961
    Abstract: A lithography method includes forming a bottom anti-reflective coating (BARC) layer on a substrate, wherein the BARC layer includes an organic polymer and a reactive chemical group having at least one of chelating ligands and capping monomers, wherein the reactive chemical group is bonded to the organic polymer; coating a metal-containing photoresist (MePR) layer on the BARC layer, wherein the MePR being sensitive to an extreme ultraviolet (EUV) radiation; performing a first baking process to the MePR layer and the BARC layer, thereby reacting a metal chemical structure of the MePR layer and the reactive chemical structure of the BARC layer and forming an interface layer between the MePR layer and the BARC layer; performing an exposure process using the EUV radiation to the MePR layer; and developing the MePR layer to form a patterned photoresist layer.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chien-Chih Chen
  • Publication number: 20230079248
    Abstract: A paper transmitting device including a feed wheel and a cleaning member is provided. The feed wheel is rotatably disposed for driving a document to move. The cleaning member is disposed on one side of the feed wheel, and has a fabric and porous structure and a woolen friction surface, so that the cleaning member contacts the feed wheel to clean the feed wheel.
    Type: Application
    Filed: September 7, 2022
    Publication date: March 16, 2023
    Inventors: Bo-Wei CHANG, Chien-Chih CHEN
  • Publication number: 20230035179
    Abstract: A display panel and a spliced display are provided. The display panel includes a substrate, a plurality of light-emitting elements, a driving circuit, and an optical sensor. The substrate includes a through hole, and the through hole includes a hole. The plurality of the light-emitting elements are disposed on the substrate. The through hole is located in a region between two of the plurality of the light-emitting elements. The driving circuit is disposed on the substrate and electrically connected to the plurality of the light-emitting elements. The optical sensor is disposed corresponding to the through hole and receives sensing light through the hole. The width W of the hole meets the equation of H?W<D. H is the depth of the hole, and D is the distance between the two of the plurality of the light-emitting elements.
    Type: Application
    Filed: October 7, 2022
    Publication date: February 2, 2023
    Applicant: Innolux Corporation
    Inventors: Chin-Lung Ting, Chien-Chih Chen, Ti Chung Chang, Chih-Chieh Wang, Jenhung Li
  • Patent number: 11553622
    Abstract: The present disclosure provides a connector assembly including a receptacle connector, a shielding shell and a heat sink. The shielding shell covers the receptacle connector. The heat sink is assembled to the shielding shell and includes a heat dissipating base plate and a heat dissipating fin soldered on the heat dissipating base plate. The heat dissipating base plate has a soldering region on which solder is provided and a recessed channel provided between a rim of the heat dissipating base plate and an outer periphery of the soldering region. The solder is provided within the soldering region in a manner such that a face of the soldering region is covered by the solder.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: January 10, 2023
    Assignee: Molex, LLC
    Inventor: Chien-Chih Chen
  • Patent number: 11531884
    Abstract: A separate quantization method of forming a combination of 4-bit and 8-bit data of a neural network is disclosed. When a training data set and a validation data set exist, a calibration manner is used to determine a threshold for activations of each of a plurality of layers of a neural network model, so as to determine how many of the activations to perform 8-bit quantization. In a process of weight quantization, the weights of each layer are allocated to 4-bit weights and 8-bit weights according to a predetermined ratio, so as to make the neural network model have a reduced size and a combination of 4-bit and 8-bit weights.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 20, 2022
    Assignee: National Chiao Tung University
    Inventors: Tien-Fu Chen, Chien-Chih Chen, Jing-Ren Chen
  • Patent number: 11526081
    Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Ming Chang, Wen Lo, Chun-Hung Liu, Chia-Hua Chang, Hsin-Wei Wu, Ta-Wei Ou, Chien-Chih Chen, Chien-Cheng Chen
  • Publication number: 20220392796
    Abstract: In an embodiment, a system includes: a cassette comprising a slit opening configured to house a wafer; a blade configured to move the wafer to and from the slit opening by extending into the slit opening, wherein a blade thickness of the blade is at most ? of a height of the slit opening and wherein the blade is configured to secure the wafer within a pocket on the blade that is at least ? of a wafer thickness of the wafer.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 8, 2022
    Inventors: Chien-Chih CHEN, Yao-Min YU, Ching-Ling LEE, Ren-Dou LEE
  • Patent number: 11523505
    Abstract: An embedded component structure includes a circuit board, an electronic component, a first conductive terminal, and a second conductive terminal. The circuit board includes a first electrical connection layer and a second electrical connection layer. The electronic component is embedded in the circuit board and includes a first contact and a second contact. The first conductive terminal and the second conductive terminal respectively at least cover a part of top surfaces and side walls of the first contact and the second contact, and the first electrical connection layer and the second electrical connection layer are respectively electrically connected to the first contact and the second contact through the first conductive terminal and the second conductive terminal. A method for manufacturing an embedded component structure is also provided.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: December 6, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Yu-Shen Chen, I-Ta Tsai, Chien-Chih Chen
  • Patent number: 11501701
    Abstract: A display panel and a spliced display are provided. The display panel includes a substrate, a plurality of light-emitting elements, a driving circuit, and an optical sensor. The substrate includes a through hole, and the through hole includes a hole. The plurality of the light-emitting elements are disposed on the substrate. The through hole is located in a region between two of the plurality of the light-emitting elements. The driving circuit is disposed on the substrate and electrically connected to the plurality of the light-emitting elements. The optical sensor is disposed corresponding to the through hole and receives sensing light through the hole. The width W of the hole meets the equation of H?W<D. H is the depth of the hole, and D is the distance between the two of the plurality of the light-emitting elements.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: November 15, 2022
    Assignee: Innolux Corporation
    Inventors: Chin-Lung Ting, Chien-Chih Chen, Ti Chung Chang, Chih-Chieh Wang, Jenhung Li
  • Publication number: 20220308567
    Abstract: A system for controlling the non-product wafer includes the following: a monitoring module, configured to monitor the state of the non-product wafer; a statistics module, configured to obtain usage information of the non-product wafer; and a control module, configured to receive a production instruction and control the non-product wafer according to the state and the usage information of the non-product wafer. The disclosure implements the purpose of automatic control and management of the non-product wafer.
    Type: Application
    Filed: March 17, 2022
    Publication date: September 29, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Wei JIANG, JU-CHIEH CHUNG, CHIEN-CHIH CHEN, Delong HUANG
  • Publication number: 20220293541
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first conductive structure disposed within a first layer of the semiconductor structure. The semiconductor structure includes a dielectric structure disposed within a second layer of the semiconductor structure, with the second layer being disposed on the first layer. The semiconductor structure includes a second conductive structure disposed within a recessed portion of the dielectric structure that extends to the first conductive structure, with the second conductive structure having a concave recessed portion on a top surface of the second conductive structure. The semiconductor structure includes multiple layers of conductive material disposed within the concave recessed portion of the second conductive structure.
    Type: Application
    Filed: October 13, 2021
    Publication date: September 15, 2022
    Inventors: Manikandan ARUMUGAM, Tsung-Yi YANG, Chien-Chih CHEN, Mu-Han CHENG, Kuo-Hsien CHENG
  • Publication number: 20220254867
    Abstract: An electronic device includes a flexible substrate and a conductive wire. The conductive wire is disposed on the flexible substrate and includes a metal portion and a plurality of openings disposed in the metal portion. The metal portion includes a plurality of extending portions and a plurality of joint portions, and each of the openings is surrounded by two of the plurality of extending portions and two of the plurality of joint portions. A ratio of a sum of widths of the plurality of extending portions to a sum of widths of the plurality of joint portions is in a range from 0.8 to 1.2.
    Type: Application
    Filed: April 28, 2022
    Publication date: August 11, 2022
    Applicant: InnoLux Corporation
    Inventors: Ya-Wen Lin, Chien-Chih Chen, Yen-Hsi Tu, Cheng-Wei Chang, Shu-Hui Yang
  • Patent number: 11380569
    Abstract: In an embodiment, a system includes: a cassette comprising a slit opening configured to house a wafer; a blade configured to move the wafer to and from the slit opening by extending into the slit opening, wherein a blade thickness of the blade is at most ? of a height of the slit opening and wherein the blade is configured to secure the wafer within a pocket on the blade that is at least ? of a wafer thickness of the wafer.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: July 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Chih Chen, Yao-Min Yu, Ching-Ling Lee, Ren-Dou Lee