Patents by Inventor Chien-Hao Wang
Chien-Hao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250041975Abstract: A laser slicing apparatus, in which a laser module provides a laser beam, and a light splitting element of a focusing lens set splits the laser beam into a plurality of focused laser beams to form a plurality of induce lines having first laser modified cracks in a modified layer at a predetermined depth inside a substrate. A rotating module rotates the light splitting element with an angle, and the light splitting element converts the focused laser beams according to this angle to form a plurality of modified groups between the induce lines. Each modified group includes a plurality of modified lines having second laser modified cracks, and the first laser modified cracks and the second laser modified cracks are connected to each other to form a continuous laser modified crack in the modified layer at the predetermined depth inside the substrate, thereby speeding up the laser slicing production.Type: ApplicationFiled: September 11, 2023Publication date: February 6, 2025Applicant: Industrial Technology Research InstituteInventors: Jyun-Jhih WANG, Chun-Ming CHEN, Yu-Chung LIN, Pin-Hao HU, Chien-Jung HUANG
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Patent number: 12211922Abstract: Gates having air gaps therein, and methods of fabrication thereof, are disclosed herein. An exemplary gate includes a gate electrode and a gate dielectric. A first air gap is between and/or separates a first sidewall of the gate electrode from the gate dielectric, and a second air gap is between and/or separates a second sidewall of the gate electrode from the gate dielectric. A dielectric cap may be disposed over the gate electrode, and the dielectric cap may wrap a top of the gate electrode. The dielectric cap may fill a top portion of the first air gap and a top portion of the second air gap. The gate may be disposed between a first epitaxial source/drain and a second epitaxial source/drain, and a width of the gate is about the same as a distance between the first epitaxial source/drain and the second epitaxial source/drain.Type: GrantFiled: July 19, 2023Date of Patent: January 28, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Ning Yao, Bo-Feng Young, Sai-Hooi Yeong, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 12205998Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.Type: GrantFiled: January 14, 2022Date of Patent: January 21, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Chien-Ning Yao, Tsung-Han Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
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Patent number: 12062596Abstract: A semiconductor device includes a substrate and a semiconductor die including an active surface with bond pads, an opposite inactive surface, and stepped side surfaces extending between the active surface and the inactive surface. The stepped side surfaces include a first planar surface extending from the inactive surface towards the active surface, a second planar surface extending from the active surface towards the inactive surface, and a side surface offset between the first planar surface and the second planar surface. The semiconductor device further includes an adhesive layer covering at least a portion of a surface area of the second surface and attaching the semiconductor die to the substrate.Type: GrantFiled: July 13, 2021Date of Patent: August 13, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rongwei Zhang, Chien Hao Wang, Bob Lee
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Publication number: 20240164021Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.Type: ApplicationFiled: January 23, 2024Publication date: May 16, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Fan CHEN, Chien-Hao WANG
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Patent number: 11882660Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.Type: GrantFiled: January 10, 2023Date of Patent: January 23, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Fan Chen, Chien-Hao Wang
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Publication number: 20230017286Abstract: A semiconductor device includes a substrate and a semiconductor die including an active surface with bond pads, an opposite inactive surface, and stepped side surfaces extending between the active surface and the inactive surface. The stepped side surfaces include a first planar surface extending from the inactive surface towards the active surface, a second planar surface extending from the active surface towards the inactive surface, and a side surface offset between the first planar surface and the second planar surface. The semiconductor device further includes an adhesive layer covering at least a portion of a surface area of the second surface and attaching the semiconductor die to the substrate.Type: ApplicationFiled: July 13, 2021Publication date: January 19, 2023Inventors: Rongwei Zhang, Chien Hao Wang, Bob Lee
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Patent number: 11553596Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.Type: GrantFiled: June 8, 2021Date of Patent: January 10, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Fan Chen, Chien-Hao Wang
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Patent number: 11421981Abstract: A method for evaluating a leadframe surface includes positioning a leadframe on a measurement apparatus at a first predetermined distance relative to an end portion of a light source of an optical sensor; irradiating a predetermined area on a surface of the leadframe with light having a single predetermined wavelength from the light source; receiving, with a light receiver of the optical sensor, reflected light from the predetermined area on the surface of the leadframe, and converting the reflected light into an electric signal; determining a reflection intensity value of the predetermined area on the surface of the leadframe based on the electric signal; and calculating a reflection ratio of the predetermined area on the surface of the leadframe based on the reflection intensity value and a predetermined reference reflection intensity value associated with the light source.Type: GrantFiled: September 10, 2019Date of Patent: August 23, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Hung-Yu Chou, Chien-Hao Wang, Tse-Tsun Chiu, Fu-Kang Lee, Liang-Kang Su
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Patent number: 11296030Abstract: An embedded component package structure including a dielectric structure, a semiconductor chip, a first polymer layer, and a patterned conductive layer is provided. The semiconductor chip is embedded in the dielectric structure. The first polymer layer covers the semiconductor chip and has a first thickness, and the first thickness is greater than a second thickness of the dielectric structure above the first polymer layer. The patterned conductive layer covers an upper surface of the dielectric structure and extends over the first polymer layer, and the patterned conductive layer is electrically connected to the semiconductor chip.Type: GrantFiled: April 29, 2019Date of Patent: April 5, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Ju Liao, Chien-Fan Chen, Chien-Hao Wang
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Embedded component package structure, embedded type panel substrate and manufacturing method thereof
Patent number: 11277917Abstract: An embedded component package structure including a circuit substrate, an embedded component and a stress compensation layer is provided. The circuit substrate includes a core layer and an asymmetric circuit structure, and the core layer has a first thickness. The embedded component is disposed in the core layer. The stress compensation layer is disposed on one side of the core layer, and the stress compensation layer has a second thickness between 4 ?m and 351 ?m.Type: GrantFiled: March 12, 2019Date of Patent: March 15, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Ju Liao, Chien-Fan Chen, Chien-Hao Wang, I-Chia Lin -
Publication number: 20210298176Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.Type: ApplicationFiled: June 8, 2021Publication date: September 23, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Fan CHEN, Chien-Hao WANG
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Patent number: 11032911Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.Type: GrantFiled: July 29, 2020Date of Patent: June 8, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Fan Chen, Chien-Hao Wang
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Patent number: 10950551Abstract: An embedded component package structure including a dielectric structure and a component is provided. The component is embedded in the dielectric structure and is provided with a plurality of conductive pillars. The conductive pillars are exposed from an upper surface of the dielectric structure and have a first thickness and a second thickness, respectively, and the first thickness is not equal to the second thickness.Type: GrantFiled: April 29, 2019Date of Patent: March 16, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Ju Liao, Chien-Fan Chen, Chien-Hao Wang
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Publication number: 20200359502Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.Type: ApplicationFiled: July 29, 2020Publication date: November 12, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Fan CHEN, Chien-Hao WANG
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Publication number: 20200343188Abstract: An embedded component package structure including a dielectric structure and a component is provided. The component is embedded in the dielectric structure and is provided with a plurality of conductive pillars. The conductive pillars are exposed from an upper surface of the dielectric structure and have a first thickness and a second thickness, respectively, and the first thickness is not equal to the second thickness.Type: ApplicationFiled: April 29, 2019Publication date: October 29, 2020Inventors: Yu-Ju LIAO, Chien-Fan CHEN, Chien-Hao WANG
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Publication number: 20200343187Abstract: An embedded component package structure including a dielectric structure, a semiconductor chip, a first polymer layer, and a patterned conductive layer is provided. The semiconductor chip is embedded in the dielectric structure. The first polymer layer covers the semiconductor chip and has a first thickness, and the first thickness is greater than a second thickness of the dielectric structure above the first polymer layer. The patterned conductive layer covers an upper surface of the dielectric structure and extends over the first polymer layer, and the patterned conductive layer is electrically connected to the semiconductor chip.Type: ApplicationFiled: April 29, 2019Publication date: October 29, 2020Inventors: Yu-Ju LIAO, Chien-Fan CHEN, Chien-Hao WANG
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EMBEDDED COMPONENT PACKAGE STRUCTURE, EMBEDDED TYPE PANEL SUBSTRATE AND MANUFACTURING METHOD THEREOF
Publication number: 20200296836Abstract: An embedded component package structure including a circuit substrate, an embedded component and a stress compensation layer is provided. The circuit substrate includes a core layer and an asymmetric circuit structure, and the core layer has a first thickness. The embedded component is disposed in the core layer. The stress compensation layer is disposed on one side of the core layer, and the stress compensation layer has a second thickness between 4 ?m and 351 ?m.Type: ApplicationFiled: March 12, 2019Publication date: September 17, 2020Inventors: Yu-Ju LIAO, Chien-Fan CHEN, Chien-Hao WANG, I-Chia LIN -
Patent number: 10757813Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.Type: GrantFiled: October 12, 2018Date of Patent: August 25, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Fan Chen, Chien-Hao Wang
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Patent number: 10726956Abstract: The fever epidemic detection system comprises a detection module, a control module and a communication module. The detection module measures and obtains a body-temperature measured value. The control module comprises a first operation unit, a determination unit and an alert unit. The first operation unit receives and calibrates the body-temperature measured value with a calibration factor, and generates a body-temperature calibrated value. The determination unit receives and determines whether the body-temperature calibrated value is within a preset normal body-temperature range and generates a determination result. The alert unit receives the determination result. The communication module transmits data to an external device. The alert unit generates a first alerting message, if the determination result shows that the body-temperature calibrated value is not within a preset normal body-temperature range.Type: GrantFiled: April 15, 2016Date of Patent: July 28, 2020Assignee: NATIONAL TAIWAN UNIVERSITYInventors: Joe-Air Jiang, Chien-Hao Wang, Ya-An Chan, Lin-Kuei Su, Cheng-Yue Liu, Po-Han Chen, Wei-Sheng Chen, Ching-Ya Tseng