Abstract: A coreless thin substrate with embedded circuits in dielectric layers is provided. The substrate includes a plurality of first patterned dielectric layers with embedded circuits, and at least a second patterned dielectric layer with embedded conducting elements. The second patterned dielectric layer is disposed between the first patterned dielectric layers, such that the embedded conducting elements electrically conduct the circuits of the first patterned dielectric layers through thermal lamination. Thus, a conventional through-hole formation process after the thermal lamination is skipped, and the substrate has a thinner and flatter profile. In one embodiment, the first patterned dielectric layers are inkjet printed layers with negative images. Moreover, the embedded circuits are flush with and exposed from an upper surface and a lower surface of the corresponding first dielectric layers.

Abstract: The present invention relates to a substrate of a window ball grid array package and a method for making the same. The substrate includes a core layer, a first conductive layer, a second conductive layer, at least one window and at least one via. The window includes a first through hole and a third conductive layer. The first through hole penetrates the substrate and has a first sidewall. The third conductive layer is disposed on the first sidewall and connects the first conductive layer and the second conductive layer. The via includes a second through hole and a fourth conductive layer. The second through hole penetrates the substrate and has a second sidewall. The fourth conductive layer is disposed on the second sidewall and connects the first conductive layer and the second conductive layer. As a result, the substrate has the effect of controlling the characteristic impedance and increasing the signal integrity.

Abstract: A circuit board process is provided. In the circuit board process, a first substrate and a second substrate are stacked to form a cavity for accommodating chips. The top of the cavity is covered by a third metal layer that serves as a mask. The first substrate has a base, a first metal layer, a second metal layer, and at least a first conductive structure passing through the base and electrically connected to the first metal layer and the second metal layer. The first metal layer is patterned to form a first circuit layer having a number of first pads. A third circuit layer having a number of third pads is formed on the second substrate. The first pads and the third pads are not on a same plane for wire bonding.

Abstract: A thermally enhanced coreless thin substrate with embedded chips, which mainly includes a patterned carrier metal layer, at least one chip, at least one dielectric layer and at least one wiring layer, is disclosed. The chip is attached to a heat sink portion of the patterned carrier metal layer. The dielectric layer is formed over the patterned carrier metal layer and covers the chip. The wiring layer is formed on the dielectric layer for electrically connecting the patterned carrier metal layer and the chip. In the process of manufacturing the thermally enhanced coreless thin substrate with embedded chips, the heat sink portion is formed by patterning the patterned carrier metal layer after finishing the formation of the wiring layer. Thus, a thin board type electronic device that combines a heat sink, a carrier substrate and embedded chips together to form an integral unit is fabricated.

Abstract: A method of fabricating a multi-chip package structure is provided. In the method, a number of cavities are formed on a predetermined cutting line of a first wafer by partly removing the first wafer and a first metal layer. Conductive walls of a first circuit layer are electrically connected to a cut cross-section of the first metal layer exposed by the cavities. In addition, conductive bumps of a second wafer are pressed into a cover layer and electrically connected to the first circuit layer. The first metal layer is then patterned to form a second circuit layer having a number of second pads. Next, the first wafer and the second wafer are cut along the predetermined cutting line to form a number of separated multi-chip package structures.

Abstract: A manufacturing process for an embedded semiconductor device is provided. In the manufacturing process, at least one insulation layer and a substrate are stacked to each other, and a third metal layer is laminated on the insulation layer to embed a semiconductor device in the insulation layer. The substrate has a base, a first circuit layer, a second circuit layer, and at least a first conductive structure passing through the base and electrically connected to the first circuit layer and the second circuit layer. In addition, the third metal layer is patterned to form a third circuit layer having a plurality of third pads.

Abstract: A surface treatment process for a circuit board is provided. The circuit board includes a substrate, a first circuit layer disposed on an upper surface of the substrate, and a second circuit layer disposed on a lower surface of the substrate. The first circuit layer is electrically connected to the second circuit layer. In the surface treatment process for the circuit board, a first oxidation protection layer and a second oxidation protection layer are respectively formed on a portion of the first circuit layer and a portion of the second circuit layer by immersion. Afterwards, the first circuit layer exposed by the first oxidation protection layer is subjected to black oxidation to form a black oxide layer. The thickness of the first oxidation protection layer is thinner than or equal to the thickness of the black oxide layer.

Abstract: A method of fabricating a substrate with an embedded component therein including the following steps is provided. First, a core layer having a first dielectric layer, a first patterned circuit layer, and a second patterned circuit layer is provided. The first patterned circuit layer and the second patterned circuit layer are disposed on an upper surface and a lower surface of the first dielectric layer, respectively. Then, a through hole is formed in the core layer. Next, the core layer is arranged on a supporting board and an embedded component having at least one electrode is disposed in the through hole. Afterward, a process of filling glue is carried out, such that the embedded component is fixed in the through hole. Thereafter, the supporting board is removed. Finally, the electrode of the embedded component is electrically connected to the second patterned circuit layer.

Abstract: A process for manufacturing a substrate with bumps is provided. First, a metallic substrate having a body and a plurality of conductive elements is provided. Next, a first dielectric layer is formed on the body, and the conductive elements are covered by the first dielectric layer. Then, a plurality of circuits and a plurality of contacts are formed on a surface of the first dielectric layer, and the contacts are electrically connected to the conductive elements. Next, a second dielectric layer is formed on the surface of the first dielectric layer, and the circuits are covered by the second dielectric layer. Finally, the body is patterned to form a plurality of bumps, and the bumps are electrically connected to the contacts by the conductive elements. The bumps are formed by etching the body, so the connection reliability between bumps and conductive elements is desirable, and the manufacturing cost is reduced.

Abstract: A method for making a circuit board includes the following steps. At least two substrates are provided, wherein each substrate includes two surfaces, two circuit layers respective formed on the two surfaces and at least a via passing through the two surfaces. A metal layer is formed on the side wall of the via, wherein the metal layer electrically connects two circuit layers on the two surfaces of each substrate to each other. An insulating film is at least formed on the surface of the metal layer by an electrophoretic deposition process. Vias of two substrates are aligned with each other and two substrates are laminated to each other, so as to form a multi-layer substrate. Another metal layer is formed on the insulating film, wherein each metal layer is an independent electrical channel.

Abstract: A multi-chip build-up package of an optoelectronic chip mainly includes a metal carrier, an IC chip, an optoelectronic chip, a build-up packaging structure including a plurality of dielectric layers and a plurality of wiring layers, and a transparent conductive substrate. The IC chip is disposed on the metal carrier and is covered by one of the dielectric layers, and a plurality of electrodes of the IC chip is electrically connected to the wiring layers. The optoelectronic chip is partially embedded in one of the dielectric layers such that an optoelectronic working region and a plurality of electrodes of the optoelectronic chip are exposed. The transparent conductive substrate is disposed on the dielectric layers and the optoelectronic chip, and the wiring layers electrically connect the optoelectronic chip and the IC chip. Accordingly, the embedded IC chip and optoelectronic chip can be electrically interconnected together in build-up process.

Abstract: A method for fabricating a circuit board comprises following steps. First, a metal substrate is provided and an electrophoretic deposition procedure is performed thereon to form an insulation film on a surface of the metal substrate. Next, a plurality of holes is formed on the insulation film to expose parts of the metal substrate. Then, a circuit layer is fabricated on the insulation film to cover the above-mentioned holes, so that the circuit layer is connected to the metal substrate through the holes. Further, a process of lithography and etching is conducted to fabricate the metal substrate into another circuit layer. Therefore, a circuit board with two circuit layers is completed.

Abstract: A manufacturing method for integrating a passive component within a substrate is disclosed. The manufacturing method comprises the steps of: providing a circuit layer, wherein a positioning blind hole is formed in the circuit layer; forming a conductive material in the positioning blind hole; positioning the passive component in the positioning blind hole of the circuit layer and electrically connecting the passive component to the circuit layer via the conductive material in the positioning blind hole; and laminating a core layer, the passive component, and the circuit layer as the substrate.

Abstract: A method for manufacturing a circuit board includes the steps of: forming a first wiring layer on a substrate; forming an insulating layer on the surface of the first wiring layer by means of electrophoretic deposition; forming a second wiring layer on the insulating layer and the surface of the substrate; and performing the follow-up procedures, such as forming a solder mask; thereby reducing the thickness of the circuit board and increasing the density of the circuit layout.

Abstract: A method for manufacturing a circuit board includes the steps of: forming a first wiring layer on a substrate; forming an insulating layer on the surface of the first wiring layer by means of electrophoretic deposition; forming a second wiring layer on the insulating layer and the surface of the substrate; and performing the follow-up procedures, such as forming a solder mask; thereby reducing the thickness of the circuit board and increasing the density of the circuit layout.

Abstract: A manufacturing process of a carrier is disclosed. First, a first substrate is provided. A circuit layer having a number of contacts is formed on a surface of the first substrate. Then, a solder mask is formed on the circuit layer and exposes the contacts. Next, a second substrate having an opening is bonded to the surface of the first substrate to form a carrier, and the opening exposes the solder mask and the contacts of the first substrate. Since the contacts are located within the opening, a circuit layout space can be increased, and a chip disposed in the opening can be electrically connected to the contacts directly, so as to reduce the thickness of a chip package structure. Besides, the carrier is formed by laminating the first and the second substrates. Hence, the manufacturing process of the carrier is simplified and yield of the carrier is promoted.

Abstract: A coreless thin substrate with embedded circuits in dielectric layers is provided. The substrate includes a plurality of first patterned dielectric layers with embedded circuits, and at least a second patterned dielectric layer with embedded conducting elements. The second patterned dielectric layer is disposed between the first patterned dielectric layers, such that the embedded conducting elements electrically conduct the circuits of the first patterned dielectric layers through thermal lamination. Thus, a conventional through-hole formation process after the thermal lamination is skipped, and the substrate has a thinner and flatter profile. In one embodiment, the first patterned dielectric layers are inkjet printed layers with negative images. Moreover, the embedded circuits are flush with and exposed from an upper surface and a lower surface of the corresponding first dielectric layers.

Abstract: A structure with a multilayer plated through hole is disclosed. At least one dielectric layer formed by deposition and a conductive layer are formed in an original plated through hole (PTH). The dielectric layer partially covers wiring layers of the substrate to electrically isolate the PTH and the conductive layer to form a multilayer PTH so as to save PTH occupation space of the substrate. Preferably, the formation of the dielectric layer is electrophoretic deposition to control the deposition thickness in the PTH very even and thin, no drilling is necessary. Accordingly, it can increase electrical performance and decrease cross-talk effect.

Abstract: A method of fabricating a substrate with an embedded component therein including the following steps is provided. First, a core layer having a first dielectric layer, a first patterned circuit layer, and a second patterned circuit layer is provided. The first patterned circuit layer and the second patterned circuit layer are disposed on an upper surface and a lower surface of the first dielectric layer, respectively. Then, a through hole is formed in the core layer. Next, the core layer is arranged on a supporting board and an embedded component having at least one electrode is disposed in the through hole. Afterward, a process of filling glue is carried out, such that the embedded component is fixed in the through hole. Thereafter, the supporting board is removed. Finally, the electrode of the embedded component is electrically connected to the second patterned circuit layer.

Abstract: A build-up package of an optoelectronic chip mainly includes a transparent circuit carrier board, at least one optoelectronic chip, at least one dielectric layer and at least one wiring layer of a build-up package. The optoelectronic chip is flip-chip bonded to the transparent circuit carrier board. The build-up package is formed on the transparent circuit carrier board, wherein the dielectric layer covers the optoelectronic chip and has a plurality of through holes, the wiring layer is formed on the dielectric layer and is electrically connected to a substrate wiring layer of the transparent circuit carrier board via the through holes. Accordingly, the build-up package of the optoelectronic chip is a thin optoelectronic product and improves the thermal dissipation, the encapsulation, and the compact of the electrical connection of the embedded optoelectronic chip.