Abstract: A thermally enhanced coreless thin substrate with embedded chips, which mainly includes a patterned carrier metal layer, at least one chip, at least one dielectric layer and at least one wiring layer, is disclosed. The chip is attached to a heat sink portion of the patterned carrier metal layer. The dielectric layer is formed over the patterned carrier metal layer and covers the chip. The wiring layer is formed on the dielectric layer for electrically connecting the patterned carrier metal layer and the chip. In the process of manufacturing the thermally enhanced coreless thin substrate with embedded chips, the heat sink portion is formed by patterning the patterned carrier metal layer after finishing the formation of the wiring layer. Thus, a thin board type electronic device that combines a heat sink, a carrier substrate and embedded chips together to form an integral unit is fabricated.