Patents by Inventor Chien Hua Chen

Chien Hua Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10933640
    Abstract: A fluid dispenser may include fluid dispensing dies in an end-to-end staggered arrangement, a non-fluid dispensing die electronic device and a molding covering the fluid dispensing dies and the electronic device.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: March 2, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chien-Hua Chen, Michael W. Cumbie
  • Patent number: 10928743
    Abstract: Embodiments herein beneficially enable simultaneous processing of a plurality of substrates in a digital direct write lithography processing system. In one embodiment a method of processing a plurality of substrate includes positioning a plurality of substrates on a substrate carrier of a processing system, positioning the substrate carrier under the plurality of optical modules, independently leveling each of the plurality of substrates, determining offset information for each of the plurality of substrates, generating patterning instructions based on the offset information for each of the plurality of substrates, and patterning each of the plurality of substrates using the plurality of optical modules. The processing system comprises a base, a motion stage disposed on the base, the substrate carrier disposed on the motion stage, a bridge disposed above a surface of the base and separated therefrom, and a plurality of optical modules disposed on the bridge.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: February 23, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chien-Hua Lai, Chia-Hung Kao, Hsiu-Jen Wang, Shih-Hao Kuo, Yi-Sheng Liu, Shih-Hsien Lee, Ching-Chang Chen, Tsu-Hui Yang
  • Patent number: 10921981
    Abstract: An electronic device includes a keyboard module, a silicone film, a light-emitting module, and a touch module. The keyboard module has a plurality of buttons and a point stick. The silicone film has a virtual touch region. The light-emitting module is configured below the silicone film and corresponds to the virtual touch region. The light-emitting module includes a first light-emitting unit and a second light-emitting unit. The touch module is configured below the silicone film and corresponds to the virtual touch region. The touch module includes a control chip and a sensing layer. The point stick, the first light-emitting unit, the second light-emitting unit, and the sensing layer are electrically connected to the control chip, respectively.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: February 16, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Meng-Huan Tsai, Yen-Hua Hsiao, Yun-Tung Pai, Chih-Yuan Lee, Chien-Hao Ho, Chia-Hua Wu, Kung-Ju Chen, Chia-Chi Lin, Chia-Chi Sun
  • Publication number: 20210039390
    Abstract: In example implementations, a method is provided, which may include providing a carrier, applying a thermal release tape over the carrier, attaching a print head die, a drive integrated circuit (IC) and an interposer on the thermal release tape, wherein the print head die comprises ink feed holes formed in a back surface of the print head die, encapsulating the print head die, the drive IC and the interposer with an epoxy molded compound (EMC), removing the carrier and the thermal release tape, and forming a slot over an area of the EMC that covers the ink feed holes, wherein the ink feed holes are to be fluidically coupled to the slot.
    Type: Application
    Filed: October 28, 2020
    Publication date: February 11, 2021
    Inventors: Michael W. Cumbie, Devin Alexander Mourey, Chien-Hua Chen
  • Publication number: 20210043719
    Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer.
    Type: Application
    Filed: October 28, 2020
    Publication date: February 11, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Hua CHEN, Teck-Chong LEE
  • Patent number: 10903561
    Abstract: A semiconductor device package includes a first glass carrier, a package body, a first circuit layer and a first antenna layer. The first circuit layer is disposed on the first surface of the first glass carrier. The first circuit layer has a redistribution layer (RDL). The package body is disposed on the first circuit layer. The package body has an interconnection structure penetrating the package body and is electrically connected to the RDL of the first circuit layer. The first antenna layer is disposed on the second surface of the first glass carrier.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: January 26, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Sheng-Chi Hsieh, Chen-Chao Wang, Teck-Chong Lee
  • Patent number: 10864719
    Abstract: Examples include a fluid ejection device comprising a molded panel, an ejection die molded in the molded panel, and an integrated circuit molded in the molded panel. The ejection die comprises ejection nozzles to selectively dispense printing material. The integrated circuit receives nozzle data and controls the selective dispensation of printing material by the ejection nozzles based at least in part on the nozzle data. The molded panel has a fluid communication channel formed therethrough and fluidly connected to the ejection die.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: December 15, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael W. Cumbie, Chien-Hua Chen, Anthony M. Fuller
  • Publication number: 20200388237
    Abstract: The present invention provides a method for transmitting data from a timing controller to a source driver, wherein the method includes the steps of: applying a plurality of data rates to a discrete data rate setting; and transmitting image data of a plurality of frames by using a plurality of modulated data rates, respectively; wherein the plurality of modulated data rates are generated by performing spread-spectrum clocking (SSC) upon the plurality of data rates, respectively; and for each of the frames, its corresponding image data is transmitting by using only one of the modulated data rates.
    Type: Application
    Filed: June 5, 2019
    Publication date: December 10, 2020
    Inventors: Mong-Hua Tu, Peng-Chi Chen, Chih-Hsiang Lin, Yin-Ho Chiang, Jen-Chieh Liu, Shih-Po Chen, Cheng-Yu Shih, Chien-Lung Cho, Yi-Ping Tu
  • Patent number: 10861840
    Abstract: An integrated passive component comprises a capacitor, a first passivation layer, an inductor, an insulation layer and an external contact. The first passivation layer surrounds the capacitor. The inductor is on the first passivation layer and electrically connected to the capacitor. The inductor comprises a plurality of conductive pillars. The insulation layer is on the first passivation layer and surrounds each of the conductive pillars. The insulation layer comprises a first surface adjacent to the first passivation layer, a second surface opposite to the first surface, and a side surface extending between the first surface and the second surface. A ratio of a width of each of the conductive pillars to a height of each of the conductive pillars is about 1:7. The external contact is electrically connected to the inductor and contacts the second surface of the insulation layer and the side surface of the insulation layer.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: December 8, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Shun Chang, Teck-Chong Lee, Chien-Hua Chen
  • Patent number: 10854458
    Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao
  • Patent number: 10850446
    Abstract: In a three-dimensional printing method example, an epoxy mold compound build material is applied. A fusing agent is selectively applied on at least a portion of the epoxy mold compound build material. The epoxy mold compound build material is exposed to energy, thereby fusing the portion of the epoxy mold compound build material in contact with the fusing agent to form a layer.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: December 1, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chien-Hua Chen, Qin Liu, Michael G. Monroe
  • Publication number: 20200369031
    Abstract: In some examples, a print bar fabrication method comprises placing printhead dies face down on a carrier, placing a printed circuit board on the carrier, wire bonding each printhead die of the printhead dies to the printed circuit board, and overmolding the printhead dies and the printed circuit board on the carrier, including fully encapsulating the wire bonds.
    Type: Application
    Filed: August 12, 2020
    Publication date: November 26, 2020
    Inventors: Silam J. Choy, Michael W. Cumbie, Devin Alexander Mourey, Chien-Hua Chen
  • Patent number: 10836169
    Abstract: In some examples, a print bar fabrication method comprises placing printhead dies face down on a carrier, placing a printed circuit board on the carrier, wire bonding each printhead die of the printhead dies to the printed circuit board, and overmolding the printhead dies and the printed circuit board on the carrier, including fully encapsulating the wire bonds.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: November 17, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Silam J. Choy, Michael W. Cumbie, Devin Alexander Mourey, Chien-Hua Chen
  • Patent number: 10836178
    Abstract: A sensing structure in an example may include at least three electrodes along an interior surface of a reservoir from a top portion of the reservoir to a bottom portion of the reservoir wherein at least one of the electrodes is closer to at least another electrode at the top portion of the reservoir than at the bottom portion of the reservoir.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: November 17, 2020
    Assignee: Hewlett Packard Develpment Company, L.P.
    Inventors: Ning Ge, Chien-Hua Chen, Michael W. Cumbie
  • Patent number: 10839899
    Abstract: A power on reset method for a resistive memory storage device is provided and includes performing a forming procedure on a memory cell of the resistive memory storage device. The forming procedure includes applying at least one forming voltage and at least one reset voltage to the memory cell. The forming procedure further includes a thermal step. The step of applying at least one reset voltage to the memory cell may be preformed before or after the thermal step. After one forming voltage is applied, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. After the thermal step, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. In addition, after one reset voltage is applied, if the memory cell passes verification, the next reset voltage is not applied to the memory cell.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 17, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Ping-Kun Wang, Shao-Ching Liao, Yu-Ting Chen, Ming-Che Lin, Chien-Min Wu, Chia-Hua Ho
  • Patent number: 10836162
    Abstract: In example implementations, an apparatus with an interposer is provided. The apparatus may include an epoxy molded compound (EMC). A print head die and a drive integrated circuit (IC) may be embedded in the EMC. An interposer may also be embedded in the EMC. The print head die, the drive IC and the interposer may be wire bonded within the EMC.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: November 17, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael W. Cumbie, Devin Alexander Mourey, Chien-Hua Chen
  • Patent number: 10833144
    Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: November 10, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Teck-Chong Lee
  • Patent number: D902981
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 24, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao
  • Patent number: D902982
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 24, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao
  • Patent number: D908775
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: January 26, 2021
    Assignee: TDK Taiwan Corp.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao