Patents by Inventor Chien-Hua Chu

Chien-Hua Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090216936
    Abstract: A data reading method suitable for a flash memory storage system having a flash memory is provided, wherein the flash memory is substantially divided into a plurality of blocks and these blocks are grouped into at least a data area and a spare area. The data reading method includes: respectively determining whether the blocks in the data area are frequently read blocks; allocating a buffer storage area corresponding to the frequently read block and copying data stored in the frequently read block to the buffer storage area; and reading the data from the buffer storage area corresponding to the frequently read block when the data stored in the frequently read block is to be read. As described above, data loss caused by read disturb can be effectively prevented.
    Type: Application
    Filed: July 23, 2008
    Publication date: August 27, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chien-Hua Chu, Wei-Chen Teo
  • Publication number: 20090198875
    Abstract: A data writing method for a flash memory is provided. The data writing method includes following steps. First, a block is selected as a substitute block from a spare area of the flash memory, wherein the substitute block is used for substituting a data block in a data area for writing a new data. Next, the new data is directly written into the substitute block starting from a start page, wherein there is valid data in the data block before the address for writing the new data. Thereby, meaningless data moving can be reduced, system performance can be improved, and overlong waiting time for writing the new data can be prevented.
    Type: Application
    Filed: March 27, 2008
    Publication date: August 6, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chien-Hua Chu, Chih-Kang Yeh, Jian-Yo Su, Jui-Hsien Chang
  • Publication number: 20090172255
    Abstract: A wear leveling method for a multi level cell (MLC) NAND flash memory is provided. The flash memory includes a first zone and a second zone respectively having a plurality of blocks, wherein each of the blocks includes an upper page and a lower page. The wear leveling method includes: respectively determining whether to start a block swapping operation of a wear leveling process in the first zone and the second zone of the flash memory according to different start-up conditions; and respectively performing the block swapping operation in the first zone and the second zone, wherein the blocks in the first zone are accessed by using only the lower pages, and the blocks in the second zone are accessed by using both the upper pages and the lower pages. Thereby, the lifespan of the flash memory is effectively prolonged and meaningless consumption of system resources is avoided.
    Type: Application
    Filed: March 12, 2008
    Publication date: July 2, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chih-Kang Yeh, Chien-Hua Chu
  • Publication number: 20090172256
    Abstract: A data writing method for a block of a multi level cell NAND flash memory including upper page addresses and lower page addresses is provided, wherein a writing speed at the lower page addresses is higher than that at the upper page addresses. The data writing method includes receiving a writing command and determining whether an address to be written with new data in the writing command is the upper page address of the block. The method also includes copying old data previously recorded on the lower page addresses of the block as an old data backup when the address to be written in the writing command is the upper page address of the block and then writing the new data to the address to be written. Thus, old data may be protected while writing data to the upper page address of the multi level cell NAND flash memory.
    Type: Application
    Filed: March 12, 2008
    Publication date: July 2, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chien-Hua Chu, Wei-Chen Teo
  • Publication number: 20090150597
    Abstract: A data writing method for a flash memory is provided. The data writing method includes: dividing a new data into at lease one sub-data by the length of a writing unit; selecting one of a plurality of spare blocks from the flash memory as a substitute block for substituting a data block, wherein the new data is to be written into the data block; sequentially writing the sub-data having the length of the writing unit into the substitute block in the writing unit; and storing the sub-data not having the length of the writing unit into a temporary area. The writing efficiency of the flash memory can be improved by temporarily storing the sub-data not having the length of the writing unit into the temporary area and then writing the sub-data not having the length of the writing unit with subsequent data into the substitute block.
    Type: Application
    Filed: March 20, 2008
    Publication date: June 11, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Jiunn-Yeong Yang, Jui-Hsien Chang, Chien-Hua Chu, Jian-Yo Su, Chih-Kang Yeh
  • Publication number: 20090106484
    Abstract: A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area.
    Type: Application
    Filed: February 4, 2008
    Publication date: April 23, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chih-Kang Yeh, Chien-Hua Chu, Jia-Yi Fu
  • Publication number: 20090094409
    Abstract: A wear leveling method for non-volatile memory is provided, by which the non-volatile memory is substantially divided into a plurality of blocks and the blocks are grouped into a data area and a spare area. The method includes selecting a block based on an erased sequence when getting the block from the spare area. The method also includes performing a wear leveling procedure.
    Type: Application
    Filed: January 22, 2008
    Publication date: April 9, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chih-Kang Yeh, Chien-Hua Chu
  • Publication number: 20090089484
    Abstract: A data protection method suitable for a plurality of physical blocks mapped to a logical block in a non-volatile memory is provided. The data protection method includes recording data update information in each of the physical blocks for identifying an update relationship of the physical blocks and re-establishing the update relationship of the physical blocks according to the data update information. The data update information is composed of a plurality of words having a circular relationship, and the number of these words is greater than the number of the physical blocks. The data update information is sequentially recorded in each of the physical blocks according to the update relationship and the circular relationship.
    Type: Application
    Filed: January 16, 2008
    Publication date: April 2, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chien-Hua Chu
  • Publication number: 20070288685
    Abstract: A flash memory scatter-write method divides a physical block of a flash memory into two areas, the first area includes a plurality of sub areas, and the second area is an area containing no data and provided for alternately writing data.
    Type: Application
    Filed: June 9, 2006
    Publication date: December 13, 2007
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chien-Hua Chu
  • Publication number: 20070226452
    Abstract: A flash storage device for transferring data to and from a host. The flash storage uses a controller to data transfer in the flash storage device, a buffer to temporarily store data for transfer between the host and the flash storage device, a first table for maintaining storage information relating to the flash storage; and a second table for maintaining information relating to the association of virtual sectors to the logical sectors, wherein the controller transfers data between the host and the flash storage and updates the first table and the second table to reflect the transfer of the data. The first table and the second table contain include addressing and status information for a more efficient and improved data transfer.
    Type: Application
    Filed: September 26, 2006
    Publication date: September 27, 2007
    Applicant: SimpleTech Global Limited
    Inventors: Chien-Hung Wu, Jen-Chieh Lou, Chien-Hua Chu, Jui-Chien Chen
  • Patent number: 7194596
    Abstract: A data management for a flash memory device is disclosed. The device includes a screen virtual sector table and a virtual unit versus physical unit table (V2P table) for each block. With the auxiliary of the screen virtual sector table and v2p table, the data programming into the target block of the flash memory is in accordance with the data receiving order, which is from lower page number to higher page number in case the target block is free. The data can be written into the target block contains data already through one or two temporal block(s). The conventional LBA data transfer protocol can still be applied to the flash memory device of this invention.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: March 20, 2007
    Assignee: SimpleTech Global Limited
    Inventors: Chien-Hung Wu, Jen-Chieh Lou, Chien-Hua Chu, Jui-Chien Chen
  • Publication number: 20050278479
    Abstract: A data management for a flash memory device is disclosed. The device includes a screen virtual sector table and a virtual unit versus physical unit table (V2P table) for each block. With the auxiliary of the screen virtual sector table and v2p table, the data programming into the target block of the flash memory is in accordance with the data receiving order, which is from lower page number to higher page number in case the target block is free. The data can be written into the target block contains data already through one or two temporal block(s). The conventional LBA data transfer protocol can still be applied to the flash memory device of this invention.
    Type: Application
    Filed: June 9, 2004
    Publication date: December 15, 2005
    Inventors: Chien-Hung Wu, Jen-Chieh Lou, Chien-Hua Chu, Jui-Chien Chen