Patents by Inventor Chien-Hua Chu
Chien-Hua Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8230161Abstract: A data backup method for backing up data temporarily stored in a cache memory of a flash memory storage device is provided, where the flash memory storage device has a plurality of physical units. The data backup method includes logically grouping a portion of the physical units into a data area and a cache area. The data backup method also includes determining whether a trigger signal is received; and when the trigger signal is received, copying the data temporarily stored in the cache memory into the cache area. Accordingly, the data backup method can quickly write the data temporarily stored in the cache memory into the physical units, thereby preventing a time out problem which may occur in the flash memory storage device.Type: GrantFiled: December 23, 2009Date of Patent: July 24, 2012Assignee: Phison Electronics Corp.Inventor: Chien-Hua Chu
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Patent number: 8225067Abstract: A multi level cell (MLC) NAND flash memory storage system is provided. A controller of the MLC NAND flash memory storage system declares it a signal level cell (SLC) NAND flash memory chip to a host system connected thereto and provides a plurality of SLC logical blocks to the host system. When the controller receives a write command and a user data from the host system, the controller writes the user data into a page of a MLC physical block and records the page of the SLC logical block corresponding to the page of the MLC physical block. When the controller receives an erase command from the host system, the controller writes a predetermined data into the page of the MLC physical block mapped to the SLC logical block to be erased, wherein the predetermined data has the same pattern as a pattern of the erased page.Type: GrantFiled: March 27, 2009Date of Patent: July 17, 2012Assignee: Phison Electronics Corp.Inventors: Chien-Hua Chu, Chih-Kang Yeh, Kok-Yong Tan
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Publication number: 20120173805Abstract: A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module.Type: ApplicationFiled: March 13, 2012Publication date: July 5, 2012Applicant: PHISON ELECTRONICS CORP.Inventors: Chien-Hua Chu, Chih-Kang Yeh
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Patent number: 8214578Abstract: A data storage method for a flash memory storage device is provided. The method includes disposing a pattern identification unit in the flash memory storage device and disposing a pattern analysis unit in a host connected to the flash memory storage device. The method further includes analyzing a usage pattern of each flash memory storage address in the flash memory storage device by using the pattern analysis unit, receiving information from the pattern analysis unit through the pattern identification unit to identify the usage pattern of each flash memory storage address, and storing data into each flash memory storage address through a corresponding process according to the usage pattern of the flash memory storage address. Thereby, data can be stored according to the usage pattern of each flash memory storage address, and accordingly the speed of storing data into the flash memory storage device can be effectively increased.Type: GrantFiled: June 19, 2009Date of Patent: July 3, 2012Assignee: Phison Electronics Corp.Inventors: Chien-Hua Chu, Shu-Hua Wang
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Patent number: 8180953Abstract: A data accessing method for accessing data in a plurality of physical page addresses of a plurality of physical blocks in a flash memory chip is provided. The data accessing method includes proving a plurality of logical page addresses for a host system, creating a logical page to physical page mapping table and a physical page to logical page mapping table to record the mapping between the logical page addresses and the physical page addresses. The data accessing method also includes writing data into the physical page addresses, and updating the logical page to physical page mapping table and the physical page to logical page mapping table. The data accessing method further includes determining whether the physical page addresses are valid or invalid based on the logical page to physical page mapping table and the physical page to logical page mapping table.Type: GrantFiled: March 4, 2009Date of Patent: May 15, 2012Assignee: Phison Electronics Corp.Inventor: Chien-Hua Chu
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Patent number: 8176267Abstract: A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module.Type: GrantFiled: September 15, 2008Date of Patent: May 8, 2012Assignee: Phison Electronics Corp.Inventors: Chien-Hua Chu, Chih-Kang Yeh
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Patent number: 8117382Abstract: A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area.Type: GrantFiled: August 22, 2011Date of Patent: February 14, 2012Assignee: Phison Electronics Corp.Inventors: Chih-Kang Yeh, Chien-Hua Chu, Jia-Yi Fu
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Patent number: 8108589Abstract: A wear leveling method for non-volatile memory is provided, by which the non-volatile memory is substantially divided into a plurality of blocks and the blocks are grouped into a data area and a spare area. The method includes selecting a block based on an erased sequence when getting the block from the spare area. The method also includes performing a wear leveling procedure.Type: GrantFiled: January 22, 2008Date of Patent: January 31, 2012Assignee: Phison Electronics Corp.Inventors: Chih-Kang Yeh, Chien-Hua Chu
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Patent number: 8103820Abstract: A wear leveling method for a multi level cell (MLC) NAND flash memory is provided. The flash memory includes a first zone and a second zone respectively having a plurality of blocks, wherein each of the blocks includes an upper page and a lower page. The wear leveling method includes: respectively determining whether to start a block swapping operation of a wear leveling process in the first zone and the second zone of the flash memory according to different start-up conditions; and respectively performing the block swapping operation in the first zone and the second zone, wherein the blocks in the first zone are accessed by using only the lower pages, and the blocks in the second zone are accessed by using both the upper pages and the lower pages. Thereby, the lifespan of the flash memory is effectively prolonged and meaningless consumption of system resources is avoided.Type: GrantFiled: March 12, 2008Date of Patent: January 24, 2012Assignee: Phison Electronics Corp.Inventors: Chih-Kang Yeh, Chien-Hua Chu
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Publication number: 20110302364Abstract: A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area.Type: ApplicationFiled: August 22, 2011Publication date: December 8, 2011Applicant: PHISON ELECTRONICS CORP.Inventors: Chih-Kang Yeh, Chien-Hua Chu, Jia-Yi Fu
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Patent number: 8074128Abstract: A block management and replacement method for a flash memory is provided. The method includes grouping physical blocks of the flash memory into physical units and dividing the physical units as a usage area and a replacement area, wherein the physical blocks grouped into the same physical unit are accessed by using a multi-planes accessing command. The method also includes when one of the physical block of the physical unit in the usage area is damaged, replacing the physical unit having the damaged physical block with one physical unit selected from the replacement area and recording the undamaged physical block within the replaced physical unit if there is an applicable physical unit in the replacement area; and replacing the damaged physical block with one physical block selected from the replacement area if there is no applicable physical unit but an undamaged physical block in the replacement area.Type: GrantFiled: December 4, 2008Date of Patent: December 6, 2011Assignee: Phison Electronics Corp.Inventors: Chien-Hua Chu, Chih-Kang Yeh, Horng-Sheng Yan
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Patent number: 8074148Abstract: A memory management method and a controller for a non-volatile memory storage device are provided. The memory management method and the controller are adapted for establishing a logical-to-physical mapping table of each block in a memory buffer of the controller by merely reading the data stored in a system management area within a start page of each block, so as to promote the management efficiency of the non-volatile memory storage device. In addition, the method and the controller of the present invention integrate all of or a part of the system management areas within the start page for efficiently managing and using the memory capacity of all the system management areas within the start page.Type: GrantFiled: August 6, 2008Date of Patent: December 6, 2011Assignee: Phison Electronics Corp.Inventors: Chien-Hua Chu, Kuo-Yi Cheng, Chih-Kang Yeh
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Patent number: 8065497Abstract: A data management method, a controller and a storage apparatus thereof are provided. The method is adapted for a storage apparatus having a plurality of blocks. Parts of the blocks are linked to configure a plurality of mother and child blocks (M&C block). The data management method includes: (a) checking whether a mother and child block currently to be written with data is the same of a mother and child block which has been most lately written with data; (b) when it is determined that the mother and child block currently to be written with data is not the same of the mother and child block which has been most lately written with data, saving a transient data of the mother and child block currently to be written with data to a mother and child block transient relationship table.Type: GrantFiled: October 27, 2008Date of Patent: November 22, 2011Assignee: Phison Electronics Corp.Inventors: Chien-Hua Chu, Chih-Kang Yeh
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Patent number: 8055873Abstract: A data writing method for a flash memory is provided. The data writing method includes following steps. First, a block is selected as a substitute block from a spare area of the flash memory, wherein the substitute block is used for substituting a data block in a data area for writing a new data. Next, the new data is directly written into the substitute block starting from a start page, wherein there is valid data in the data block before the address for writing the new data. Thereby, meaningless data moving can be reduced, system performance can be improved, and overlong waiting time for writing the new data can be prevented.Type: GrantFiled: March 27, 2008Date of Patent: November 8, 2011Assignee: Phison Electronics Corp.Inventors: Chien-Hua Chu, Chih-Kang Yeh, Jian-Yo Su, Jui-Hsien Chang
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Patent number: 8055837Abstract: A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area.Type: GrantFiled: October 1, 2010Date of Patent: November 8, 2011Assignee: Phison Electronics Corp.Inventors: Chih-Kang Yeh, Chien-Hua Chu, Jia-Yi Fu
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Patent number: 8046528Abstract: A data writing method for a block of a multi level cell NAND flash memory including upper page addresses and lower page addresses is provided, wherein a writing speed at the lower page addresses is higher than that at the upper page addresses. The data writing method includes receiving a writing command and determining whether an address to be written with new data in the writing command is the upper page address of the block. The method also includes copying old data previously recorded on the lower page addresses of the block as an old data backup when the address to be written in the writing command is the upper page address of the block and then writing the new data to the address to be written. Thus, old data may be protected while writing data to the upper page address of the multi level cell NAND flash memory.Type: GrantFiled: March 12, 2008Date of Patent: October 25, 2011Assignee: Phison Electronics Corp.Inventors: Chien-Hua Chu, Wei-Chen Teo
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Patent number: 8037232Abstract: A data protection method suitable for a plurality of physical blocks mapped to a logical block in a non-volatile memory is provided. The data protection method includes recording data update information in each of the physical blocks for identifying an update relationship of the physical blocks and re-establishing the update relationship of the physical blocks according to the data update information. The data update information is composed of a plurality of words having a circular relationship, and the number of these words is greater than the number of the physical blocks. The data update information is sequentially recorded in each of the physical blocks according to the update relationship and the circular relationship.Type: GrantFiled: January 16, 2008Date of Patent: October 11, 2011Assignee: Phison Electronics Corp.Inventor: Chien-Hua Chu
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Publication number: 20110231732Abstract: An error correcting method for a memory chip is provided. The memory chip has a plurality of physical blocks, each of the physical blocks has a plurality of physical pages, and the physical pages belonging to the same physical block are individually written and simultaneously erased. The error correcting method includes sequentially writing a plurality of data into the physical pages of a first physical block and generating a parity information according to the data. The error correcting method further includes writing the parity information into one of the physical pages of the first physical block following the data and correcting the data in the first physical block according to the parity information. Accordingly, the parity information can be used for correcting error bits in the data when an error checking and correcting circuit can not correct the error bits. Thereby, the error correcting ability is enhanced.Type: ApplicationFiled: May 24, 2010Publication date: September 22, 2011Applicant: PHISON ELECTRONICS CORP.Inventor: Chien-Hua Chu
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Publication number: 20110202690Abstract: A data writing method for writing data from a host system into a plurality of memory dies of a rewritable non-volatile memory storage apparatus is provided. The data writing method includes determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard. The data writing method also includes using a general mode to write the data into the memory dies when the data transmission interface of the host system complies with the first interface standard and using a power saving mode to write the data into the memory dies when the data transmission interface of the host system complies with the second interface standard. Accordingly, the data writing method can effectively prevent the stability of the rewritable non-volatile memory storage apparatus from reducing due to insufficient power supplied by the data transmission interface.Type: ApplicationFiled: April 21, 2010Publication date: August 18, 2011Applicant: PHISON ELECTRONICS CORP.Inventors: Chien-Hua Chu, Hong-Lipp Ko
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Patent number: 8001317Abstract: A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area.Type: GrantFiled: February 4, 2008Date of Patent: August 16, 2011Assignee: Phison Electronics Corp.Inventors: Chih-Kang Yeh, Chien-Hua Chu, Jia-Yi Fu