Patents by Inventor Chien-hung Chen

Chien-hung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210320406
    Abstract: An antenna system and an electronic device are provided. The antenna system includes a first substrate, a first antenna group, and a second antenna group. The first antenna group includes four first antennas that are disposed on a peripheral area of the first substrate. The second antenna group includes four second antennas that are disposed in an array on a second substrate. The four second antennas of the second antenna group are disposed above a central area of the first substrate. The central area of the first substrate has a recess. The second substrate is disposed above the recess. A first predetermined distance is defined between a bottom of the second substrate and the recess of the first substrate. A second predetermined distance is defined between the second substrate and the first substrate. The first predetermined distance is greater than the second predetermined distance.
    Type: Application
    Filed: August 11, 2020
    Publication date: October 14, 2021
    Inventors: CHIEN-HUNG CHEN, CHIH-HSIN WU, YU-YUAN GUO
  • Publication number: 20210320210
    Abstract: A semiconductor device includes a substrate, a semiconductor layer, a gate structure, source/drain regions, a bottom isolation layer, and a bottom spacer. The semiconductor layer is above the substrate. The gate structure is above the substrate and surrounds the semiconductor layer. The source/drain regions are on opposite sides of the semiconductor layer. The bottom isolation layer is between the substrate and the semiconductor layer. The bottom spacer is on a sidewall of the bottom isolation layer.
    Type: Application
    Filed: April 13, 2020
    Publication date: October 14, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang LIN, Shih-Cheng CHEN, Jung-Hung CHANG, Lo-Heng CHANG, Chien-Ning YAO
  • Patent number: 11145475
    Abstract: A keyboard device includes plural key structures. Each key structure includes a plate assembly, a keycap, a connecting member and a buffering element. The plate assembly has a hollow region. The keycap is located over the plate assembly. The connecting member is connected between the keycap and the plate assembly. The keycap is connected with the connecting member through at least one hook of the keycap. The keycap is movable upwardly or downwardly relative to the plate assembly through the connecting member. The buffering element is installed on the plate assembly. The buffering element is extended in a direction toward the keycap and penetrated through the hollow region of the plate assembly. While the keycap is moved downwardly and the at least one hook of the keycap is contacted with the buffering element, there is the gap between the keycap and the plate assembly.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: October 12, 2021
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Ming-Han Wu, Che-Wei Yang, Yi-Wei Chen, Chien-Hung Liu, Chen-Hsuan Hsu
  • Patent number: 11140983
    Abstract: A slide rail assembly includes a first rail, a second rail displaceable with respect to the first rail, a third rail displaceable with respect to the second rail, a working member movably mounted on the second rail and switchable between two states, and a contact feature on the third rail. The third rail can be displaced from a retracted position to an extended position in a first direction, and when the third rail is displaced from the extended position to the retracted position in a second direction, the contact feature is brought into contact with the working member in one of the two states so as to drive and thereby retract the second rail with respect to the first rail in the second direction.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: October 12, 2021
    Assignees: King Slide Works Co., Ltd., King Slide Technology Co., Ltd.
    Inventors: Ken-Ching Chen, Shih-Lung Huang, Chien-Hung Kuo, Chun-Chiang Wang
  • Patent number: 11144198
    Abstract: A control method of a touch display apparatus applicable to a probe station is provided. The probe station includes a movable element. The movable element is a chuck stage, a camera stage, a probe platen, or a positioner. The control method of a touch display apparatus includes displaying a first window and a second window on a touch display apparatus; displaying an operation interface on the first window and displaying a real-time image on the second window; and detecting a touch instruction generated on the operation interface, where the movable element moves according to the touch instruction.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: October 12, 2021
    Assignee: MPI CORPORATION
    Inventors: Chien-Hung Chen, Guan-Jhih Liou, Lin-Lin Chih, Stojan Kanev
  • Patent number: 11145474
    Abstract: A keyboard device includes plural key structures. Each key structure includes a supporting plate, a keycap, a connecting member and a hook element. The keycap is located over the supporting plate, and movable upwardly or downwardly relative to the supporting plate. The connecting member is connected between the supporting plate and the keycap. The hook element is installed on the supporting plate. The connecting member is connected with the supporting plate through the hook element. The supporting plate is made of a first material with a first specific gravity. The hook element is made of a second material with a second specific gravity. The second specific gravity is higher than the first specific gravity.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: October 12, 2021
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Chin-Sung Pan, Chien-Hung Liu, Lei-Lung Tsai, Sheng-Fan Chang, Tsu-Yi Chen, Chun-Yuan Liu
  • Patent number: 11145789
    Abstract: A light-emitting device includes a substrate including a top surface; a semiconductor stack including a first semiconductor layer, an active layer and a second semiconductor layer formed on the substrate, wherein a portion of the top surface is exposed; a distributed Bragg reflector (DBR) formed on the semiconductor stack and contacting the portion of the top surface of the substrate; a metal layer formed on the distributed Bragg reflector (DBR), contacting the portion of the top surface of the substrate and being insulated with the semiconductor stack; and an insulation layer formed on the metal layer and contacting the portion of the top surface of the substrate.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: October 12, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Che-Hung Lin, Chien-Chih Liao, Chi-Shiang Hsu, De-Shan Kuo, Chao-Hsing Chen
  • Publication number: 20210313441
    Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Inventors: Chien-Chih Lin, Yen-Ting Chen, Wen-Kai Lin, Szu-Chi Yang, Shih-Hao Lin, Tsung-Hung Lee, Ming-Lung Cheng
  • Patent number: 11127703
    Abstract: Semiconductor devices are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump. The spacer surrounds the bump and disposed between the etching stop layer and the bump.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Yu Ku, Cheng-Lung Yang, Chen-Shien Chen, Hon-Lin Huang, Chao-Yi Wang, Ching-Hui Chen, Chien-Hung Kuo
  • Patent number: 11126050
    Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: September 21, 2021
    Assignee: Au Optronics Corporation
    Inventors: Min-Tse Lee, Sheng-Yen Cheng, Yueh-Hung Chung, Kuang-Hsiang Liao, Yang-Chun Lee, Yan-Kai Wang, Ya-Ling Hsu, Yi-Ren Chen, Hung-Che Lin, Sheng-Ju Ho, Chien-Huang Liao, Chen-Hsien Liao
  • Patent number: 11126051
    Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: September 21, 2021
    Assignee: Au Optronics Corporation
    Inventors: Min-Tse Lee, Sheng-Yen Cheng, Yueh-Hung Chung, Kuang-Hsiang Liao, Yang-Chun Lee, Yan-Kai Wang, Ya-Ling Hsu, Yi-Ren Chen, Hung-Che Lin, Sheng-Ju Ho, Chien-Huang Liao, Chen-Hsien Liao
  • Publication number: 20210287726
    Abstract: A memory macro includes a first memory cell array, a first tracking circuit, a first and a second transistor. The first memory cell array includes rows of memory cells and columns of memory cells. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first control signal, a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, and a first tracking bit line coupled to the first and second set of memory cells. The first set of pull-down cells or loading cells is configured to track a memory cell of the first memory cell array. The first and second transistor are coupled to the first tracking bit line, and configured to charge the first tracking bit line to a pre-charge voltage level responsive to a tracking enable signal.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 16, 2021
    Inventors: Chien-Kuo SU, Chiting CHENG, Pankaj AGGARWAL, Yen-Huei CHEN, Cheng Hung LEE, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG, Jhon Jhy LIAW
  • Patent number: 11120868
    Abstract: A semiconductor memory device comprising a plurality of memory cells configured to store digital data and an input multiplexer configured to enable the selection of a particular memory cell from the plurality of memory cells. The semiconductor memory device further comprises a read/write driver circuit configured to read data from the selected memory cell and write data to the selected memory cell, and a write logic block configured to provide logical control to the read/write driver circuit for writing data to the selected of memory cell. The read/write driver circuit may be coupled to the read/write input multiplexer by a data line and an inverted data line and the read and the write operations to the selected memory cell occur over the same data line and inverted data line.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Yuan Chen, Che-Ju Yeh, Hau-Tai Shieh, Cheng Hung Lee, Hung-Jen Liao, Sahil Preet Singh, Manish Arora, Hemant Patel, Li-Wen Wang
  • Publication number: 20210280521
    Abstract: A substrate structure is disclosed. The substrate structure includes a carrier, a dielectric layer on the carrier, a patterned organic core layer in the dielectric layer, and a conductive via. The patterned organic core layer defines a passage extending in the dielectric layer towards the carrier. The conductive via extends through the passage towards the carrier without contacting the patterned organic core layer.
    Type: Application
    Filed: March 9, 2020
    Publication date: September 9, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Fan CHEN, Yu-Ju LIAO, Chu-Jie YANG, Sheng-Hung SHIH
  • Patent number: 11114060
    Abstract: A cursor image detection comparison and feedback status determination method is disclosed. The method is based on a non-invasive data-extraction system architecture, and uses an image processing unit to perform detection comparison on a cursor image shown on an operation screen outputted from a machine controller. The method includes steps of obtaining cursor foreground and background images set by a user, and selecting an algorithm to process the cursor foreground and background images to generate a cursor mask, and reading a cursor image and applying the cursor mask on the cursor image for pattern comparison, transmitting information of a comparison result and a cursor feedback status to a software control system, so as to provide a correction system to perform a cursor process program and check whether the movement of the cursor meet a position controlled by a feedback and correction system, thereby completing closed-loop control for the cursor.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: September 7, 2021
    Assignee: ADLINK TECHNOLOGY INC.
    Inventors: Chao-Tung Yang, Wei-Hung Chen, Shih-Hsun Lin, Wei-Jyun Tu, Chun-Hong Liu, Chien-Chung Lin, Chieh-Yuan Lo, Hsiao-Ling Chang
  • Publication number: 20210273080
    Abstract: In an embodiment, a device includes: a substrate; a first semiconductor layer extending from the substrate, the first semiconductor layer including silicon; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer including silicon germanium, edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, the second germanium concentration being less than the first germanium concentration, the edge portions of the second semiconductor layer including sides and a top surface of the second semiconductor layer; a gate stack on the second semiconductor layer; lightly doped source/drain regions in the second semiconductor layer, the lightly doped source/drain regions being adjacent the gate stack; and source and drain regions extending into the lightly doped source/drain regions.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Inventors: Che-Yu Lin, Chien-Hung Chen, Wen-Chu Hsiao
  • Publication number: 20210268555
    Abstract: A plasma ashing method is provided. The plasma ashing method includes analyzing the process status of each of a number of semiconductor substrate models undergoing a tested plasma ash process by a residue gas analyzer. The tested plasma ash processes for the semiconductor substrate models utilize a plurality of tested recipes. The plasma ashing method further includes selecting one of the tested recipes as a process recipe for a plasma ash process.
    Type: Application
    Filed: May 21, 2021
    Publication date: September 2, 2021
    Inventors: Chun-Jen HSIAO, Ya-Ping CHEN, Chien-Hung LIN, Wen-Pin LIU, Chin-Wen CHEN
  • Patent number: 11088028
    Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Yu Lin, Chien-Wei Lee, Chien-Hung Chen, Wen-Chu Hsiao, Yee-Chia Yeo
  • Patent number: 11078915
    Abstract: A contra-rotating fan structure includes a first base, a first fan, a second base, and a second fan. The first fan is rotatably disposed on the first base and includes a first hub. The first hub has a first largest width. The second fan is rotatably disposed on the second base and includes a second hub. The second hub has a second largest width. The first base and the second base are located between the first fan and the second fan. The second largest width is greater than the first largest width.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: August 3, 2021
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chien-Hung Chen, Chao-Fu Yang, Chien-Chih Huang, Yueh-Lung Huang, Shun-Chen Chang
  • Patent number: 11074376
    Abstract: A method for analyzing a process output and a method for creating an equipment parameter model are provided. The method for analyzing the process output includes the following steps: A plurality of process steps are obtained. A processor obtains a step model set including a plurality of first step regression models, each of which represents a relationship between N of the process steps and a process output. The processor calculates a correlation of each of the first step regression models. The processor picks up at least two of the first step regression models to be a plurality of second step regression models whose correlations are ranked at top among the correlations of the first step regression models. The processor updates the step model set by a plurality of third step regression models, each of which represents a relationship between M of the process steps and the process output.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: July 27, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Ching Cheng, Chun-Liang Hou, Chien-Hung Chen, Wen-Jung Liao, Min-Chin Hsieh, Da-Ching Liao, Li-Chin Wang