Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: A reference voltage generator circuit includes: a first transistor and a second transistor, wherein the first transistor and the second transistor are coupled with each other and are located on a substrate, wherein the first transistor has a first conduction threshold voltage and a first rated voltage, wherein the second transistor has a second conduction threshold voltage and a second rated voltage, wherein the first rated voltage is higher than the second rated voltage; wherein the reference voltage generator circuit is configured to generate a bandgap reference voltage with temperature compensation according to a difference between the first conduction threshold voltage and the second conduction threshold voltage.

Abstract: A positioning method and probe system for performing the same, a method for operating probe system, and a method for utilizing probe system to produce a tested semiconductor device are provided. The positioning method is used for positioning a plurality of probe assemblies with an under-test device including a plurality of pads, each of the probe assemblies have at least one probe tip that corresponds to each of the pads for contact, and at least one fixed probe assembly and at least one motorized probe assembly are defined among the probe assemblies during a positioning process.

Abstract: A fan includes a frame, an impeller and a motor. The impeller includes a hub, a plurality of blades, first air-guiding plates and second air-guiding plates. The hub has a tapered shape. A width of the hub gradually increases along a direction from a top portion of the hub to a bottom portion of the hub. The hub has at least an air vent. The blades are disposed around an outer periphery of the hub. The first air-guiding plates and the second air-guiding plates are disposed around an inner periphery of the hub. The first air-guiding plates are arranged between two of the second air-guiding plates in staggered. The second air-guiding plates are arranged between two of the first air-guiding plates in staggered. The first air-guiding plates and the second air-guiding plates have different thicknesses, heights or shapes.

Abstract: A method of fabricating a semiconductor device includes recessing an upper portion of a first dielectric layer disposed over a conductive feature. The method includes filling the recessed upper portion with a second dielectric layer to form a void embedded in the second dielectric layer. The method includes etching the second dielectric layer and the first dielectric layer to form a contact opening that exposes at least a portion of the conductive feature using the void to vertically align at least a lower portion of the contact opening with the conductive feature. The method includes filling the contact opening with a conductive material to form a contact feature electrically coupled to the conductive feature.

Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.

Abstract: A die bonding tool includes a bond head that secures a semiconductor die against a planar surface of the bond head, an actuator system that moves the bond head and the semiconductor die towards a surface of a target substrate, and at least one contact sensor configured to detect an initial contact between a first region of the semiconductor die and the surface of the target substrate, where in response to detecting the initial contact between the semiconductor die and the target substrate, the actuator tilts the planar surface of the bond head and the semiconductor die to bring a second region of the semiconductor die into contact with the surface of the target substrate and thereby provide improved contact between the semiconductor die and the target substrate and more effective bonding including instances where the planar surface of the bond head and the target substrate surface are not parallel.

Abstract: A wafer grinding parameter optimization method and an electronic device are provided. The method includes the following. A natural frequency of a grinding wheel spindle of wafer processing equipment is obtained, and a grinding stability lobe diagram is generated accordingly. A grinding speed is selected based on a speed range of the grinding wheel spindle. Multiple grinding parameter combinations are determined based on the grinding speed. Multiple grinding simulation result combinations corresponding to the grinding parameter combinations are generated. A specific grinding parameter combination is selected based on each of the grinding simulation result combinations, and the wafer processing equipment is set accordingly.

Abstract: A display device is provided. The display device includes a first electrode and a second electrode. The first electrode includes a first main portion, a first peripheral portion, and a plurality of first extending portions. Part of the first extending portions extend into the first peripheral portion and are connected to each other via a first vertically-extending portion. Other part of the first extending portions do not extend into the first peripheral portion and are separated from each other. The second electrode includes a second main portion, a second peripheral portion, and a plurality of second extending portions. Part of the second extending portions extend into the second peripheral portion and are connected to each other via a second vertically-extending portion. Other part of the second extending portions do not extend into the second peripheral portion and are separated from each other.

Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.

Abstract: A method of fabricating a semiconductor device includes recessing an upper portion of a first dielectric layer disposed over a conductive feature. The method includes filling the recessed upper portion with a second dielectric layer to form a void embedded in the second dielectric layer. The method includes etching the second dielectric layer and the first dielectric layer to form a contact opening that exposes at least a portion of the conductive feature using the void to vertically align at least a lower portion of the contact opening with the conductive feature. The method includes filling the contact opening with a conductive material to form a contact feature electrically coupled to the conductive feature.

Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.

Abstract: A lens assembly includes a first lens, a second lens, a third lens, a fourth lens, a fifth lens, and a sixth lens, wherein the first, second, third, fourth, fifth, and sixth lenses are arranged in order from an object side to an image side along an optical axis. The first lens is a meniscus lens with positive refractive power and includes a convex surface facing the object side and a concave surface facing the image side. The second, third, and fourth lenses are with refractive power. The fifth lens is with positive refractive power and includes a convex surface facing the image side. The sixth lens is with negative refractive power and includes a concave surface facing the image side. The lens assembly satisfies: 3<D1/T6<9; wherein D1 is an effective optical diameter of the convex surface of the first lens and T6 is a thickness of the sixth lens.

Abstract: The present disclosure provides a method, a system and a kit for assessing the homologous recombination deficiency (HRD) status of a subject. The present disclosure further provides a method, a system and a kit for identifying a treatment based on the HRD status for the human subject.

Abstract: A lens device includes a lens module, an image forming unit and a light path turning module. The lens module includes one or plural lenses. The light path turning module is disposed between the lens module and the image forming unit. The light exiting from the lens module is reflected at least twice by the light path turning module.

Abstract: A lens assembly includes a lens unit and a first reflective element. The lens unit includes a plurality of lenses and the back focal length of the lens unit is longer than the total length of the lens unit. The first reflective element includes a first surface, a first prism surface, and a bottom surface, and the first prism surface connects the first surface and the bottom surface, respectively. The lens unit and the first reflective element are arranged in order from an object side along a first axis. A light from the object side enters the first reflective element from the first surface and then guided to the first prism surface.

Abstract: The invention provides a semiconductor structure, which comprises a first standard cell and a second standard cell located on a substrate, wherein an isolation region is included between the first standard cell and the second standard cell, a plurality of fin structures and a plurality of gates form a plurality of transistors, which are respectively located in the first standard cell and the second standard cell, and a plurality of single diffusion breaks (SDBs) located in the first standard cell and the second standard cell. A plurality of first dummy grooves in the first standard cell and the second standard cell, and a plurality of second dummy grooves in the isolation region, wherein some of the second dummy grooves overlap the first dummy grooves.

Abstract: An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes first gate lines arranged along a first direction and extending along a second direction. The second standard cell abuts to one side of the first standard cell along the second direction and includes second gate lines arranged along the first direction and extending along the second direction. A first gate line width of the first gate lines and a second gate line width of the second gate lines are different. A first cell width of the first standard cell and a second cell width of the second standard cell are integral multiples of a default gate line pitch of the first gate lines and the second gate lines. At least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.

Abstract: A camera device includes a plurality of lenses and an annular body. The annular body is disposed between the object side and the plurality of lenses, between the plurality of lenses, or between the plurality of lenses and the image side. The annular body includes an annular main body, an outer circumferential portion, and an inner circumferential portion, wherein the annular main body connects to the outer circumferential portion and the inner circumferential portion, the annular main body is disposed between the outer circumferential portion and the inner circumferential portion, and the inner circumferential portion is non-circular and surrounds the optical axis to form a hole. The camera device satisfies: Dx>Dy; where Dx is a maximum dimension of the hole through which the optical axis passes, and Dy is a minimum dimension of the hole through which the optical axis passes.

Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.