Abstract: A tooth surface laser processing method and a laser processing system for the same are provided. The laser processing method adapted for a tooth comprises the following steps. The tooth is first checked up to obtain tooth information so that one may determine whether the tooth is suitable for laser processing steps. A laser processing system is chosen according to the tooth information, and laser parameters are selected and loaded according to the part on the surface of the tooth and the degree required to be processed. The laser processing steps are performed on the surface of the tooth by the laser processing system to form a laser processed structure on the surface of the tooth. The laser processed structure comprises a plurality of micro-grooves and a plurality of micro-bumps therebetween.

Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.

Abstract: The present application relates to the technical field of semiconductors, and in particular, to a wafer scheduling method and a wafer scheduling apparatus for an etching equipment. The wafer scheduling method includes: obtaining a wafer processing request, where the wafer processing request includes at least process information of wafers and an equipment processing parameter of the etching equipment; responding to the wafer processing request, and determining a wafer scheduling parameter corresponding to the process information and the equipment processing parameter, based on the process information, the equipment processing parameter, and a preset wafer scheduling policy, where the wafer scheduling parameter is used to determine a transfer time for transferring the wafers to the etching equipment for processing; and performing wafer scheduling processing on the wafers by using the wafer scheduling parameter. In this way, the wafer processing productivity of the etching equipment can be improved.

Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes first and second gates, a dielectric hump, a first spacer, a charge storage layer, a gate dielectric layer, a high-k layer and doped regions. The first and the second gates are disposed on a substrate. The dielectric hump is disposed on the substrate between the first gate and the second gate. The first spacer is disposed on a sidewall of the dielectric hump. The charge storage layer is disposed between the first gate and the substrate. The gate dielectric layer is disposed between the second gate and the substrate. The high-k layer is disposed between the first gate and the charge storage layer and between the second gate and the gate dielectric layer. The doped regions are disposed in the substrate at two sides of the first gate and at two sides of the second gate.

Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes a substrate having first and second regions, first and second isolation structures in the substrate, a charge storage layer on the substrate, first and second gates and doped regions. The first isolation structures define first active areas in the first region. A top surface of the first isolation structure is higher than that of the substrate. The second isolation structures define second active areas in the second region. A top surface of the second isolation structure is lower than that of the substrate. The first gate is on the charge storage layer in the first active area. The second gate is on the charge storage layer in the second active area. The doped regions are in the substrate at two sides of the first gate and at two sides of the second gate.

Abstract: A lens assembly includes a lens unit and a first reflective element. The lens unit includes a plurality of lenses and the back focal length of the lens unit is longer than the total length of the lens unit. The first reflective element includes a first surface, a first prism surface, and a bottom surface, and the first prism surface connects the first surface and the bottom surface, respectively. The lens unit and the first reflective element are arranged in order from an object side along a first axis. A light from the object side enters the first reflective element from the first surface and then guided to the first prism surface.

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes a package substrate and a semiconductor device mounted on the surface of the package substrate. A first ring is disposed over the surface of the package substrate and surrounds the semiconductor device. A second ring is disposed over the top surface of the first ring. Also, a protruding part and a matching recessed part are formed on the top surface of the first ring and the bottom surface of the second ring, respectively. The protruding part extends into and engages with the recessed part to connect the first ring and the second ring. An adhesive layer is disposed between the surface of the package substrate and the bottom surface of the first ring for attaching the first ring and the overlying second ring to the package substrate.

Abstract: The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region; forming an isolation feature in the trench; performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and forming a cladding layer of the second semiconductor material over the silicon nitride layer.

Abstract: A computing environment determines whether one or more file systems associated with an application allow for modification of a file access time of an associated file and whether a kernel updates, in at least one case, the file access time upon accessing the associated file. The associated file is at least one file managed by the one or more file systems. The computing environment determines files accessed by the application using a technique selected based on whether the one or more file systems allow for modification of the file access time or whether the kernel updates, in the at least one case, the file access time upon accessing the associated file. The computing environment provides an output representing the files accessed by the application.

Abstract: A computing environment determines, by an initialization process, a monitor instance identifier of an instance of an application, wherein the initialization process initializes monitoring of the instance of the application. The computing environment generates, by the initialization process, a system call argument based on a pseudo-randomly generated identifier. The computing environment makes, by the initialization process, a system call comprising the system call argument. The computing environment determines, by a kernel-space Berkeley packet filter (BPF), to monitor the instance of the application based on the system call. The computing environment extracts, by the kernel-space BPF, the pseudo-randomly generated identifier from the system call argument to obtain the monitor instance identifier. The computing environment stores, in a watch list, the monitor instance identifier and the pseudo-randomly generated identifier.

Abstract: In an embodiment, a device includes a substrate, a first semiconductor layer that extends from the substrate, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes silicon and the second semiconductor layer includes silicon germanium, with edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, and the second germanium concentration being less than the first germanium concentration. The device also includes a gate stack on the second semiconductor layer, lightly doped source/drain regions in the second semiconductor layer, and source and drain regions extending into the lightly doped source/drain regions.

Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.

Abstract: The present invention provides a method for forming a layout pattern of static random access memory, comprising forming a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

Abstract: A wide-angle lens assembly includes a first, a second, a third, a fourth, a fifth, a sixth, a seventh, and an eighth lenses, all of which are orderly arranged from an object side to an image side along an optical axis. The first, fourth, fifth, seventh, and eighth lenses are with refractive power. The second, third, and sixth lenses are with positive refractive power. The wide-angle lens assembly satisfies at least one of the following conditions: 0.8?f/D22?3; 0.025 degrees?1?1/??0.3 degrees?1; 0.03 degrees?1?1/??0.35 degrees?1; 0.5??/??30; wherein f is an effective focal length of the wide-angle lens assembly, D22 is an effective optical diameter of an image side surface of the second lens, ? is a maximum tangent angle of a first cemented surface, and ? is a maximum tangent angle of a second cemented surface.

Abstract: A laser colored product, a laser coloring method therefor, and a laser coloring system using the same are provided. The laser coloring method comprises the following steps. First, provide a processing workpiece which includes a processing part, and the processing part includes a pattern region. The processing part within the pattern region includes an inner portion and an outer layer, and the outer layer includes metal materials. Use the laser coloring system to irradiate the outer layer of the pattern region in stages to convert the outer layer of the pattern region into a metal color pattern layer. The metal color pattern layer includes metal materials or metal compounds of metal materials, and the metal color pattern layer includes a plurality of pixel units arranged in arrays, wherein each of the pixel units includes a pixel color, and each of the pixel units has a pixel width or a pixel length between 1 ?m to 500 ?m.

Abstract: The present invention provides a layout pattern of static random access memory, comprising a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

Abstract: A semiconductor device includes a circuit substrate, at least one semiconductor die, a first frame, and a second frame. The at least one semiconductor die is connected to the circuit substrate. The first frame is disposed on the circuit substrate and encircles the at least one semiconductor die. The second frame is stacked on the first frame. The first frame includes a base portion and an overhang portion. The base portion has a first width. The overhang portion is disposed on the base portion and has a second width greater than the first width. The overhang portion laterally protrudes towards the at least one semiconductor die with respect to the base portion. The first width and the second width are measured in a protruding direction of the overhang portion.

Abstract: A package structure is provided. The package structure includes a substrate and a chip-containing structure over the substrate. The package structure also includes a warpage-control element laterally surrounding the chip-containing structure. The warpage-control element has a protruding portions extending into the substrate.

Abstract: A grinding apparatus and a crystal orientation adjustment fixture thereof are provided. The crystal orientation adjustment fixture includes a fixing seat, an adjustment body, a first adjustment component, and a universal mandrel module. The adjustment body is assembled to the fixing seat through a rear end surface thereof. The adjustment body has a universal slot recessed in a front end surface thereof and a first adjustment slot formed along an adjustment direction, and a bottom of the first adjustment slot corresponds in position to the fixing seat. The first adjustment component is movably assembled in the first adjustment slot along the adjustment direction and abuts against the fixing seat. The universal mandrel module is rotatably assembled in the universal slot. The first adjustment component is adjustable along the adjustment direction to move the adjustment body relative to the fixing seat along the adjustment direction.