Patents by Inventor Chien-hung Chen

Chien-hung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240019681
    Abstract: A lens device includes a lens module, an image forming unit and a light path turning module. The lens module includes one or plural lenses. The light path turning module is disposed between the lens module and the image forming unit. The light exiting from the lens module is reflected at least twice by the light path turning module.
    Type: Application
    Filed: June 16, 2023
    Publication date: January 18, 2024
    Inventors: Guo-Quan Lin, Hsi-Ling Chang, Chien-Hung Chen, Bo-Yan Chen, Ming-Huang Tseng, Ming-Wei Shih
  • Publication number: 20240006405
    Abstract: The invention provides a semiconductor structure, which comprises a first standard cell and a second standard cell located on a substrate, wherein an isolation region is included between the first standard cell and the second standard cell, a plurality of fin structures and a plurality of gates form a plurality of transistors, which are respectively located in the first standard cell and the second standard cell, and a plurality of single diffusion breaks (SDBs) located in the first standard cell and the second standard cell. A plurality of first dummy grooves in the first standard cell and the second standard cell, and a plurality of second dummy grooves in the isolation region, wherein some of the second dummy grooves overlap the first dummy grooves.
    Type: Application
    Filed: July 28, 2022
    Publication date: January 4, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hsien Lin, Chien-Hung Chen, Ruei-Yau Chen
  • Patent number: 11862622
    Abstract: An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes first gate lines arranged along a first direction and extending along a second direction. The second standard cell abuts to one side of the first standard cell along the second direction and includes second gate lines arranged along the first direction and extending along the second direction. A first gate line width of the first gate lines and a second gate line width of the second gate lines are different. A first cell width of the first standard cell and a second cell width of the second standard cell are integral multiples of a default gate line pitch of the first gate lines and the second gate lines. At least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: January 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Yuan Wu, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Chien-Hung Chen, Chun-Hsien Lin
  • Patent number: 11852849
    Abstract: A camera device includes a plurality of lenses and an annular body. The annular body is disposed between the object side and the plurality of lenses, between the plurality of lenses, or between the plurality of lenses and the image side. The annular body includes an annular main body, an outer circumferential portion, and an inner circumferential portion, wherein the annular main body connects to the outer circumferential portion and the inner circumferential portion, the annular main body is disposed between the outer circumferential portion and the inner circumferential portion, and the inner circumferential portion is non-circular and surrounds the optical axis to form a hole. The camera device satisfies: Dx>Dy; where Dx is a maximum dimension of the hole through which the optical axis passes, and Dy is a minimum dimension of the hole through which the optical axis passes.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: December 26, 2023
    Assignees: SINTAI OPTICAL (SHENZHEN) CO., LTD., ASIA OPTICAL CO., INC.
    Inventors: Ming-Wei Shih, Hsi-Ling Chang, Chien-Hung Chen
  • Patent number: 11854929
    Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Lin, Chin-Hua Wang, Shu-Shen Yeh, Chien-Hung Chen, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20230411234
    Abstract: A device includes a package substrate, an interposer having a first side bonded to the package substrate, a first die bonded to a second side of the interposer, the second side being opposite the first side, a ring on the package substrate, wherein the ring surrounds the first die and the interposer; and a heat spreader over and coupled to the ring and the first die, wherein a first coefficient of thermal expansion of a first material of the ring and a second coefficient of thermal expansion of a second material of the heat spreader are different, and wherein in a cross-sectional view a combined structure of the heat spreader and the ring have a H-shaped profile.
    Type: Application
    Filed: May 26, 2022
    Publication date: December 21, 2023
    Inventors: Shu-Shen Yeh, Yu Chen Lee, Po-Chen Lai, Po-Yao Lin, Shin-Puu Jeng, Yu-Sheng Lin, Chien-Hung Chen
  • Publication number: 20230402402
    Abstract: A semiconductor package including a recessed stiffener ring and a method of forming are provided. The semiconductor package may include a substrate, a semiconductor die bonded to the substrate, an underfill between the semiconductor die and the substrate, and a stiffener ring attached to the substrate, wherein the stiffener ring encircles the semiconductor die in a top view. The stiffener ring may include a recess that faces the semiconductor die.
    Type: Application
    Filed: May 17, 2022
    Publication date: December 14, 2023
    Inventors: Shu-Shen Yeh, Chien Hung Chen, Ming-Chih Yew, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20230386991
    Abstract: A semiconductor device includes a circuit substrate, at least one semiconductor die, a first frame, and a second frame. The at least one semiconductor die is connected to the circuit substrate. The first frame is disposed on the circuit substrate and encircles the at least one semiconductor die. The second frame is stacked on the first frame. The first frame includes a base portion and an overhang portion. The base portion has a first width. The overhang portion is disposed on the base portion and has a second width greater than the first width. The overhang portion laterally protrudes towards the at least one semiconductor die with respect to the base portion. The first width and the second width are measured in a protruding direction of the overhang portion.
    Type: Application
    Filed: August 2, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hung Chen, Shu-Shen Yeh, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20230378024
    Abstract: A ring structure on a package substrate is divided into at least four different components, including a plurality of first pieces and a plurality of second pieces. By dividing the ring structure into at least four different components, the ring structure reduces flexibility of the package substrate, which thus reduces stress on a molding compound (e.g., in a range from approximately 1% to approximately 10%). As a result, molding cracking is reduced, which reduces defect rates and increases yield. Accordingly, raw materials, power, and processing resources are conserved that would otherwise be consumed with manufacturing additional packages when defect rates are higher.
    Type: Application
    Filed: May 17, 2022
    Publication date: November 23, 2023
    Inventors: Yu-Sheng LIN, Chien Hung CHEN, Po-Chen LAI, Chin-Hua WANG, Shin-Puu JENG
  • Patent number: 11823991
    Abstract: A semiconductor device includes a circuit substrate, at least one semiconductor die, a first frame, and a second frame. The at least one semiconductor die is connected to the circuit substrate. The first frame is disposed on the circuit substrate and encircles the at least one semiconductor die. The second frame is stacked on the first frame. The first frame includes a base portion and an overhang portion. The base portion has a first width. The overhang portion is disposed on the base portion and has a second width greater than the first width. The overhang portion laterally protrudes towards the at least one semiconductor die with respect to the base portion. The first width and the second width are measured in a protruding direction of the overhang portion.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hung Chen, Shu-Shen Yeh, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20230343858
    Abstract: In an embodiment, a device includes a substrate, a first semiconductor layer that extends from the substrate, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes silicon and the second semiconductor layer includes silicon germanium, with edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, and the second germanium concentration being less than the first germanium concentration. The device also includes a gate stack on the second semiconductor layer, lightly doped source/drain regions in the second semiconductor layer, and source and drain regions extending into the lightly doped source/drain regions.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 26, 2023
    Inventors: Che-Yu Lin, Chien-Hung Chen, Wen-Chu Hsiao
  • Publication number: 20230326881
    Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes a package substrate and a semiconductor device mounted on the surface of the package substrate. A first ring is disposed over the surface of the package substrate and surrounds the semiconductor device. A second ring is disposed over the top surface of the first ring. Also, a protruding part and a matching recessed part are formed on the top surface of the first ring and the bottom surface of the second ring, respectively. The protruding part extends into and engages with the recessed part to connect the first ring and the second ring. An adhesive layer is disposed between the surface of the package substrate and the bottom surface of the first ring for attaching the first ring and the overlying second ring to the package substrate.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 12, 2023
    Inventors: Chien Hung Chen, Shu-Shen Yeh, Po-Chen Lai, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20230298851
    Abstract: A charged particle beam apparatus for inspecting a sample is provided. The apparatus includes a pixelized electron detector to receive signal electrons generated in response to an incidence of an emitted charged particle beam onto the sample. The pixelized electron detector includes multiple pixels arranged in a grid pattern. The multiple pixels may be configured to generate multiple detection signals, wherein each detection signal corresponds to the signal electrons received by a corresponding pixel of the pixelized electron detector. The apparatus further includes a controller includes circuitry configured to determine a topographical characteristic of a structure within the sample based on the detection signals generated by the multiple pixels, and identifying a defect within the sample based on the topographical characteristic of the structure of the sample.
    Type: Application
    Filed: July 26, 2021
    Publication date: September 21, 2023
    Applicant: ASML Netherlands B.V.
    Inventors: Chih-Yu JEN, Chien-Hung CHEN, Long MA, Bruno LA FONTAINE, Datong ZHANG
  • Publication number: 20230290747
    Abstract: Embodiments provide metal features which dissipate heat generated from a laser drilling process for exposing dummy pads through a dielectric layer. Because the dummy pads are coupled to the metal features, the metal features act as a heat dissipation feature to pull heat from the dummy pad. As a result, reduction in heat is achieved at the dummy pad during the laser drilling process.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 14, 2023
    Inventors: Chien-Hung Chen, Cheng-Pu Chiu, Chien-Chen Li, Chien-Li Kuo, Ting-Ting Kuo, Li-Hsien Huang, Yao-Chun Chuang, Jun He
  • Publication number: 20230253344
    Abstract: A package structure is provided. The package structure includes a substrate and a chip-containing structure bonded to the substrate. The package structure also includes a warpage-control element attached to the substrate. The warpage-control element has a protruding portion extending into the substrate.
    Type: Application
    Filed: April 21, 2023
    Publication date: August 10, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng LIN, Chien-Hung CHEN, Po-Chen LAI, Po-Yao LIN, Shin-Puu JENG
  • Patent number: 11721644
    Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes a package substrate and a semiconductor device mounted on the surface of the package substrate. A first ring is disposed over the surface of the package substrate and surrounds the semiconductor device. A second ring is disposed over the top surface of the first ring. Also, a protruding part and a matching recessed part are formed on the top surface of the first ring and the bottom surface of the second ring, respectively. The protruding part extends into and engages with the recessed part to connect the first ring and the second ring. An adhesive layer is disposed between the surface of the package substrate and the bottom surface of the first ring for attaching the first ring and the overlying second ring to the package substrate.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien Hung Chen, Shu-Shen Yeh, Po-Chen Lai, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11721745
    Abstract: In an embodiment, a device includes a substrate, a first semiconductor layer that extends from the substrate, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes silicon and the second semiconductor layer includes silicon germanium, with edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, and the second germanium concentration being less than the first germanium concentration. The device also includes a gate stack on the second semiconductor layer, lightly doped source/drain regions in the second semiconductor layer, and source and drain regions extending into the lightly doped source/drain regions.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Yu Lin, Chien-Hung Chen, Wen-Chu Hsiao
  • Publication number: 20230238058
    Abstract: When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.
    Type: Application
    Filed: February 24, 2022
    Publication date: July 27, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Jen-Yang Hsueh, Ling-Hsiu Chou, Chih-Yang Hsu
  • Publication number: 20230230661
    Abstract: A method and a system used to determine microsatellite instability (MSI) status utilizing Next-Generation Sequencing (NGS) and a machine learning model are disclosed. The present disclosure further provides a method and a system for identifying a treatment based on the computed MSI status data for the human subject.
    Type: Application
    Filed: June 18, 2021
    Publication date: July 20, 2023
    Inventors: YA-CHI YEH, CHIEN-HUNG CHEN, SHU-JEN CHEN, YING-JA CHEN, KUAN-YING CHEN
  • Publication number: 20230230935
    Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.
    Type: Application
    Filed: March 21, 2023
    Publication date: July 20, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Ching, Shu-Shen Yeh, Chien-Hung Chen, Hui-Chang Yu, Yu-Min Cheng