Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.

Abstract: A semiconductor inspecting method for ensuring a scrubbing length on a pad includes following steps. First off, a first position of a probe needle from above is defined. In addition, a wafer comprising at least a pad is placed on a wafer chuck of a semiconductor inspecting system. Thereafter, a relative vertical movement between the probe needle and the pad is made by adopting a driving system of the semiconductor inspecting system to generate a scrubbing length on the pad. Next, whether the scrubbing length is equal to or larger than a preset value or not is recognized by adopting the vision system and the relative vertical movement is stopped by adopting the driving system.

Abstract: The semiconductor inspecting method includes following steps. First, a first position of a probe needle from above is defined by adopting a vision system of a semiconductor inspecting system. Then, a first relative vertical movement between the probe needle and the pad is made by adopting a driving system of the semiconductor inspecting system. Thereafter, a minimum change in position of the probe needle corresponding to the first position is recognized by adopting the vision system of the semiconductor inspecting system. Next, the first relative vertical movement is stopped by adopting the driving system of the semiconductor inspecting system.

Abstract: The present invention provides a layout pattern of static random access memory, comprising a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

Abstract: A method includes receiving a physical circuit design file that includes physical circuit partitions that are each mapped to a respective chip. The physical circuit partitions are connected to one another by a respective timing path having an original delay. The method further includes determining a slack budget of the respective timing path, and determining a delay upper bound value based on a shortest timing path delay and the slack budget. Further, the method includes updating the delay upper bound of the respective timing path based on the slack budget, assigning an interconnection delay upper bound to a physical interconnection between at least two chips based on the updated slack budget of the respective timing path, determining a multiplexing data ratio (XDR) based on at least the interconnection delay upper bound of the physical interconnection, and performing routing between the at least two chips based on the XDR.

Abstract: A package structure and a formation method of a package structure are provided. The package structure includes a circuit substrate and a die package bonded to the circuit substrate through bonding structures. The package structure also includes a warpage-control element attached to the circuit substrate. The warpage-control element has a protruding portion extending into the circuit substrate. The warpage-control element has height larger than that of the die package.

Abstract: The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region; forming an isolation feature in the trench; performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and forming a cladding layer of the second semiconductor material over the silicon nitride layer.

Abstract: A lens assembly includes a first lens, a second lens, a third lens, and a fourth lens. The first lens is with positive refractive power and includes a concave surface facing an object side and a convex surface facing an image side. The second lens is with negative refractive power and includes a concave surface facing the object side. The third lens is with positive refractive power. The fourth lens is with refractive power and includes a concave surface facing the image side. The first lens, the second lens, the third lens, and the fourth lens are arranged in order from the object side to the image side along an optical axis. The lens assembly satisfies: TTL/f>1.2; wherein TTL is a total length of optical system of the lens assembly and f is an effective focal length of the lens assembly.

Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.

Abstract: A lens assembly includes a first, second, third, and fourth in order from an object side to an image side along an optical axis. The first lens is a meniscus lens with positive refractive power and includes a convex surface facing the object side and a concave surface facing the image side. The second lens is with negative refractive power. The third lens is with positive refractive power. The fourth lens is a meniscus lens with refractive power. The lens assembly satisfies at least one of following conditions: ?0.1?R11/R42?0.53; 2?TTL/SD4?7; 0.1?SD1/f?0.6.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.

Abstract: A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are extended in width or length to connect to the power rail and the ground rail of the other one of the standard cells.

Abstract: A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are shifted to align and connect to the power rail and the ground rail of the other one of the standard cells.

Abstract: A method for fabricating a static random access memory (SRAM) includes the steps of: forming a gate structure on a substrate; forming an epitaxial layer adjacent to the gate structure; forming a first interlayer dielectric (ILD) layer around the gate structure; transforming the gate structure into a metal gate; forming a contact hole exposing the epitaxial layer, forming a barrier layer in the contact hole, forming a metal layer on the barrier layer, and then planarizing the metal layer and the barrier layer to form a contact plug. Preferably, a bottom portion of the barrier layer includes a titanium rich portion and a top portion of the barrier layer includes a nitrogen rich portion.

Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.

Abstract: A package structure and a formation method of a package structure are provided. The package structure includes a circuit substrate and a die package bonded to the circuit substrate through bonding structures. The package structure also includes a warpage-control element attached to the circuit substrate. The warpage-control element has a protruding portion extending into the circuit substrate. The warpage-control element has height larger than that of the die package.

Abstract: The present application relates to the technical field of semiconductors, and in particular, to a wafer scheduling method and a wafer scheduling apparatus for an etching equipment. The wafer scheduling method includes: obtaining a wafer processing request, where the wafer processing request includes at least process information of wafers and an equipment processing parameter of the etching equipment; responding to the wafer processing request, and determining a wafer scheduling parameter corresponding to the process information and the equipment processing parameter, based on the process information, the equipment processing parameter, and a preset wafer scheduling policy, where the wafer scheduling parameter is used to determine a transfer time for transferring the wafers to the etching equipment for processing; and performing wafer scheduling processing on the wafers by using the wafer scheduling parameter. In this way, the wafer processing productivity of the etching equipment can be improved.

Abstract: A method for removing nodule defects is disclosed. The nodule defects may be formed on a non-selected portion of a semiconductor structure during formation of a semiconductor region on a selected portion of the semiconductor structure. A plasma having a higher selectivity to etch the nodule defects relative to the semiconductor region may be used to selectively remove the nodule defects on the non-selected portion.

Abstract: A package assembly includes a package substrate, a package lid located on the package substrate and including a plate portion, an outer foot extending from the plate portion, and an inner foot having a height greater than or equal to a height of the outer foot, extending from the plate portion and including a first inner foot corner portion located inside a first corner of the outer foot, and an adhesive that adheres the outer foot to the package substrate and adheres the inner foot to the package substrate.

Abstract: A method for fabricating a static random access memory (SRAM) includes the steps of: forming a gate structure on a substrate; forming an epitaxial layer adjacent to the gate structure; forming a first interlayer dielectric (ILD) layer around the gate structure; transforming the gate structure into a metal gate; forming a contact hole exposing the epitaxial layer, forming a barrier layer in the contact hole, forming a metal layer on the barrier layer, and then planarizing the metal layer and the barrier layer to form a contact plug. Preferably, a bottom portion of the barrier layer includes a titanium rich portion and a top portion of the barrier layer includes a nitrogen rich portion.