Patents by Inventor Chien-hung Chen

Chien-hung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • GENERATING A SEMICONDUCTOR COMPONENT LAYOUT
    Publication number: 20150356235
    Abstract: A method includes generating a first set of configurations of a layout of semiconductor components. The configurations of the first set of configurations each satisfy a first sub-set of a set of design rules. The method also includes generating a second set of configurations of the layout of semiconductor components. The second set of configurations are generated by eliminating one or more configurations of the first set of configurations based on a determination that the eliminated one or more configurations of the first set of configurations fail to satisfy a second sub-set of the set of design rules. The method further includes manufacturing a semiconductor device having semiconductor components arranged based on one of the configurations of the second set of configurations.
    Type: Application
    Filed: August 19, 2015
    Publication date: December 10, 2015
    Inventors: Chien-Hung CHEN, Yung-Chow PENG, Chung-Hui CHEN, Chih-Ming YANG
  • PLANAR DESIGN TO NON-PLANAR DESIGN CONVERSION METHOD
    Publication number: 20150356231
    Abstract: A planar design to non-planar design conversion method includes following steps. At least a diffusion region pattern including a first side and a second side perpendicular to each other is received. A look-up table is queried to obtain a first positive integer according to the first side of the diffusion region pattern and a second positive integer according to the second side of the diffusion region pattern. Then, a plurality of fin patterns is formed. An amount of the fin patterns is equal to the second positive integer. The fin patterns respectively include a first fin length, and the first fin length is a product of the first positive integer and a predetermined value. The forming is performed by at least a computer-aided design (CAD) tool.
    Type: Application
    Filed: July 21, 2014
    Publication date: December 10, 2015
    Inventors: Chao-Yao Chiang, Kuo-Hsun Huang, Chien-Hung Chen
  • CLOCK SKEW ADJUSTING STRUCTURE
    Publication number: 20150355672
    Abstract: An clock skew adjusting structure is provided. The clock skew adjusting structure includes a substrate, a wiring structure, a first active component and a second active component. The wiring structure includes at least a wiring layer and at least a via, the via is configured for different wiring layers to be electrically connected with each other. The first active component is formed on the substrate and configured for delivering a clock signal to the wiring structure. The second active component is formed on the substrate and electrically connected to the first active component through the wiring structure thus forming a timing path. The second active component receives the clock signal through the timing path.
    Type: Application
    Filed: August 6, 2015
    Publication date: December 10, 2015
    Inventor: Chien-Hung CHEN
  • Energy Saving Device of Air Compressor
    Publication number: 20150338025
    Abstract: An energy saving for an air compressor is provided, including an inlet end of an inlet pipe being provided with an air filter, a connection end of the inlet pipe being connected to an inlet side of a compressor, an outlet side of the compressor being provided with an outlet pipe, an outlet end of the outlet pipe being connected to an air reservoir, an air supply side of the air reservoir being provided with an air supply pipe, mainly in that one or more accelerated pressurization pipes may be concatenated on the inlet pipe or outlet pipe or air supply pipe, the interior of the accelerated pressurization pipe is a through hole, the inner peripheral surface of the through hole is provided with several spiral grooves thereon, as an air flows through said accelerated pressurization pipe, the air flow is guided by the several spiral grooves naturally to rotate.
    Type: Application
    Filed: May 23, 2014
    Publication date: November 26, 2015
    Inventors: NAN-CHI CHEN, WANG-CHUN CHEN, CHIEN-HUNG CHEN
  • Energy Saving Device for Accelerated Pressurization in Injection Molding Machine
    Publication number: 20150336317
    Abstract: An energy saving device for accelerated pressurization in an injection molding machine includes a mold needing vapor and cooled water or oil in an injection molding process. The cooled water or oil is provided by a pump, followed by connecting to the mold through a water or oil supply pipeline. The interior of the accelerated pressurization energy saving pipe is a through hole. Three or more spiral grooves are provided on the inner peripheral surface of the through hole and having an angle rotated in a front direction, with the lateral direction of each spiral groove having an inclined angle. The vapor or water or oil enforces angle rotation and inclined angle accelerated pressurization.
    Type: Application
    Filed: May 23, 2014
    Publication date: November 26, 2015
    Inventors: Nan-Chi Chen, Wan-Chun Chen, Chien-Hung Chen
  • BACK PLATE ASSEMBLY AND BACKLIGHT MODULE
    Publication number: 20150338573
    Abstract: A back plate assembly and a backlight module are provided. The back plate assembly includes a back plate, at least one optical film and at least one fixing member. The back plate includes a bottom plate and a sidewall. The optical film is disposed on the bottom plate. The fixing member includes a main body and a protruding member. At least one portion of the main body overlaps with the sidewall. The protruding member is disposed on the main body and is combined with the optical film.
    Type: Application
    Filed: October 29, 2014
    Publication date: November 26, 2015
    Inventors: Min-Jui KAO, Yung-Chieh CHAO, Teng-Yi HUANG, Chien-Hung CHEN
  • Lens Assembly
    Publication number: 20150331224
    Abstract: A lens assembly includes a first lens, a second lens, a third lens, a fourth lens and a fifth lens, all of which are arranged in sequence from an object side to an image side along an optical axis. The first lens is with refractive power and includes a convex surface facing the object side. The second and third lenses are with refractive power. The fourth lens is with refractive power and includes a convex surface facing the image side. The fifth lens is with negative refractive power. The lens assembly satisfies: 0?f1/f2?6, (Vd1+Vd2)/2>40, Vd1?Vd3, Vd2?Vd3, Vd5?Vd3 wherein f1 is an effective focal length of the first lens, f2 is an effective focal length of the second lens and Vd1, Vd2, Vd3, Vd5 are Abbe numbers of the first, second, third, fifth lenses.
    Type: Application
    Filed: April 27, 2015
    Publication date: November 19, 2015
    Inventors: Po-Yuan Shih, Chien-Hung Chen, Hsi-Ling Chang
  • Liquid crystal display panel
    Patent number: 9182637
    Abstract: A liquid crystal display panel comprise a first substrate, a second substrate and a electrode structure. The electrode structure is disposed on the first substrate. The electrode structure further comprises a first sub-electrode having a first stem electrode with a first end edge and a first branch electrode nearest the first end edge, and a second sub-electrode having a second stem electrode with a second end edge and a second branch electrode nearest the second end edge. The first sub-electrode and the second sub-electrode are adjacent to each other, and the first end edge are adjacent to the second end edge. A first distance between the first end edge and the first branch electrode is different from a second distance between the second end edge and the second branch electrode.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: November 10, 2015
    Assignee: INNOLUX CORPORATION
    Inventors: Chien-Hung Chen, Ching-Che Yang
  • PIXEL STRUCTURE AND LIQUID CRYSTAL DISPLAY STRUCTURE USING THE SAME
    Publication number: 20150309378
    Abstract: A pixel structure substrate including a substrate, a first dielectric layer and a second dielectric layer is provided. A data line and a first electrode are disposed on the substrate. The first dielectric layer directly covers the data line. The second dielectric layer covers the first electrode and the first dielectric layer. A thickness of the second dielectric layer is smaller than a thickness of the first dielectric layer, and the following equation is satisfied u1*A1/d1<u2*A2/d2, wherein A1 denotes an area of the first dielectric layer overlapping the data line, d1 denotes the thickness of the first dielectric layer and u1 denotes a permittivity of the first dielectric layer, A2 denotes an area of the second dielectric layer overlapping the pixel electrode, d2 denotes the thickness of the second dielectric layer and u2 denotes a permittivity of the second dielectric layer.
    Type: Application
    Filed: July 2, 2015
    Publication date: October 29, 2015
    Inventors: Chien-Hung CHEN, Pi-Ying CHUANG, Chuan-Chung WANG, Yu-Wei CHEN
  • Liquid-crystal panel and the UV curing method thereof
    Patent number: 9164305
    Abstract: This disclosure provides a LC panel and the UV curing method therein for the LC curing treatment. The LC panel includes: a first substrate with a plurality of protrusion electrodes formed thereon; a second substrate disposed on the first substrate; a LC layer interposed between the first and second substrates; and a deflecting structure disposed between the first and second substrates and configured for changing optical paths of UV light; wherein the UV light passes through the areas between the neighboring protrusion electrodes, and the deflecting structure is located in the optical paths of the UV light.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: October 20, 2015
    Assignee: INNOLUX CORPORATION
    Inventors: Yu-Wei Chen, Pi-Ying Chuang, Chien-Hung Chen
  • Method of designing fin-based transistor for power optimization
    Patent number: 9158886
    Abstract: A method of designing a fin-based transistor for power optimization includes following steps. A planar field-effect transistor (planar-FET) design including a plurality of planar semiconductor devices is received. An initial fin field-effect transistor (FinFET) design including a plurality of fin-based semiconductor devices corresponding to the planar semiconductor devices is generated. A timing analysis is performed to the initial FinFET design to recognize at least a critical path and at least a non-critical path in the initial FinFET design. The non-critical path includes at least one of the fin-based semiconductor devices. The fin-based semiconductor device on the non-critical path is adjusted and thus a refined FinFET design is generated. A current required by the refined FinFET design is lower than a current required by the initial FinFET design.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: October 13, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chien-Hung Chen
  • Semiconductor structure and manufacturing method thereof
    Patent number: 9147767
    Abstract: A semiconductor structure includes a substrate and a metal gate. The metal gate includes a metallic filling layer and disposed over the substrate. The semiconductor structure further includes a dielectric material over the metallic filling layer and separating the metallic filling layer from a conductive trace. The conductive trace is over the dielectric material. The semiconductor structure further includes a conductive plug extending longitudinally through the dielectric material and ending with a lateral encroachment inside the metallic filling layer along a direction. The lateral direction is substantially perpendicular to the longitudinal direction of the conductive plug.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: September 29, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chien-Hung Chen, Shen-Chieh Liu, Hobin Chen, Wen-Lang Wu, Cherng-Chang Tsuei
  • Verifying method of optical proximity correction
    Patent number: 9147035
    Abstract: A verifying method of an optical proximity correction is provided. The verifying method includes the following steps. A first netlist file is extracted from an integrated pre-OPC layout. A first post-OPC layout and a second post-OPC layout are merged to be an integrated post-OPC layout. A second netlist file is extracted from the integrated post-OPC layout. The first netlist file and the second netlist are compared.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: September 29, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Hsun Huang, Chao-Yao Chiang, Chien-Hung Chen
  • Generating a semiconductor component layout
    Patent number: 9141754
    Abstract: A method comprises generating a first set of configurations of a layout of semiconductor components. The configurations of the first set of configurations each satisfy a first sub-set of a set of design rules. The method also comprises generating a second set of configurations of the layout of semiconductor components. The second set of configurations are generated by eliminating one or more configurations of the first set of configurations based on a determination that the eliminated one or more configurations of the first set of configurations fail to satisfy a second sub-set of the set of design rules. The method further comprises selecting a layout generation configuration for generating the layout of semiconductor components. The method additionally comprises generating the layout of semiconductor components based on the selected layout generation configuration.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: September 22, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hung Chen, Yung-Chow Peng, Chung-Hui Chen, Chih-Ming Yang
  • Display device and manufacturing method thereof
    Patent number: 9140924
    Abstract: A display device having a plurality of pixel units and a manufacturing method of the same are provided. The display device includes a first substrate assembly, a second substrate assembly, a liquid crystal mixture, and a pillared polymer network. The first substrate assembly includes a first substrate and a first electrode layer disposed on the first substrate. The second substrate assembly includes a second substrate. The liquid crystal mixture is disposed between the first and second substrate assemblies. The pillared polymer network is disposed between the first and second substrate assemblies and has a first end and second end. The first end abuts against the first substrate assembly and is disposed correspondingly to the first electrode layer. The second end abuts against the second substrate assembly. Each of the pixel units includes the pillared polymer network.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 22, 2015
    Assignee: INNOLUX CORPORATION
    Inventors: Chien-Hung Chen, Chuan-Chung Wang, Pi-Ying Chuang, Li-Chieh Hsu
  • Clock skew adjusting method and structure
    Patent number: 9135389
    Abstract: A clock transmission adjusting method applied to integrated circuit design is provided. The clock transmission adjusting method includes the following steps. At first, a timing path including a clock source and a sequential logic cell is provided. Then, at least one non-active wire delay module is inserted in the timing path to approach a predetermined clock arrival time. An integrated circuit structure utilizing the clock transmission adjusting method is also provided.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: September 15, 2015
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventor: Chien-Hung Chen
  • Memory cell structure and method for forming the same
    Patent number: 9136276
    Abstract: A method for forming a memory cell structure includes following steps. A substrate including at least a memory cell region defined thereon is provided, and a first gate stack is formed in the memory cell region. A first LDD implantation is performed to form a first LDD at one side of the first gate stack in the memory cell region, and the first LDD includes a first conductivity type. A second LDD implantation is performed to form a second LDD at one side of the first gate stack opposite to the first LDD in the memory cell region, and the second LDD includes the first conductivity type. The first LDD and the second LDD are different from each other.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: September 15, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Huei Huang, Sung-Bin Lin, Wen-Chung Chang, Feng-Ji Tsai, Yen-Ting Ho, Chien-Hung Chen
  • Lens Assembly
    Publication number: 20150241661
    Abstract: A lens assembly includes five lenses, a second lens, a third lens, a fourth lens and a fifth lens. The first lens is with positive refractive power. The second lens is with negative refractive power. The third lens is with positive refractive power. The fourth lens is a concave-convex lens and includes a concave surface facing the object side and a convex surface facing the image side. The fifth lens includes a concave surface facing the image side. The first lens and the third lens are made of the same material and an Abbe number of the first lens is the same as an Abbe number of the third lens. An Abbe number of the first lens, an Abbe number of the third lens and an Abbe number of the fifth lens are greater than an Abbe number of the second lens.
    Type: Application
    Filed: February 11, 2015
    Publication date: August 27, 2015
    Inventors: Po-Yuan Shih, Hsi-Ling Chang, Chien-Hung Chen
  • Phase-locked loop start up circuit
    Patent number: 9112507
    Abstract: A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator (VCO) having a VCO input for receiving a control voltage and a VCO output, a feedback loop between the VCO input and the VCO output, and a start-up circuit having a start-up circuit input and a start-up circuit output. The start-up circuit output is coupled to the VCO input and the start-up circuit input is coupled to the VCO output. The start-up circuit provides a voltage at its start-up circuit output during a start-up phase, which terminates after a predetermined number of feedback pulses are detected by the start-up circuit.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: August 18, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Hung Chen, Mao-Hsuan Chou, Tsung-Hsien Tsai
  • Bicycle fitting method for producing bicycle, bicycle fitting system and computer program product
    Patent number: 9108694
    Abstract: A bicycle fitting method for producing a bicycle is provided. The method includes the steps of receiving a bicycle riding information and a body measurement corresponding to a cyclist. According to the bicycle riding information, a bicycle model is provided. According to the body measurement and the selected bicycle model, a bicycle frame size and a set of bicycle geometric adjustment parameters are provided. According to the bicycle model, the bicycle frame size, and the set of bicycle geometric adjustment parameters, a bicycle which fits the cyclist is produced.
    Type: Grant
    Filed: May 28, 2012
    Date of Patent: August 18, 2015
    Assignee: Giant Manufacturing Co., Ltd.
    Inventors: Chien-Hung Chen, Wei-Chieh Ho