Abstract: A method includes generating a first set of configurations of a layout of semiconductor components. The configurations of the first set of configurations each satisfy a first sub-set of a set of design rules. The method also includes generating a second set of configurations of the layout of semiconductor components. The second set of configurations are generated by eliminating one or more configurations of the first set of configurations based on a determination that the eliminated one or more configurations of the first set of configurations fail to satisfy a second sub-set of the set of design rules. The method further includes manufacturing a semiconductor device having semiconductor components arranged based on one of the configurations of the second set of configurations.

Abstract: A method for manufacturing a printed circuit board is disclosed, which comprises the following steps. A basic board having an upper surface and a bottom surface opposite to the upper surface is provided. A plurality of the electronic components temporarily disposed on the basic board is provided. At least one locating pin temporarily disposed on a place of the basic board is provided, in which the electronic components are not temporarily disposed on the place. Surface mount technology is used simultaneously to joint at least one locating pin and the electronic components on the basic board.

Abstract: An integrated circuit layout structure having dual-height standard cells includes at least a first standard cell including a first cell height and at least a second standard cell including a second cell height. The second cell height is one half of the first cell height. The first standard cell includes at least one or more first doped region formed in a middle of the first standard cell and a plurality of second doped regions formed at a top side and a bottom side of the first standard cell. The first doped region includes a first conductivity type and the second doped regions include a second conductivity type complementary to the first conductivity type.

Abstract: A gate structure is provided. The gate structure includes a substrate, a gate disposed on the substrate and a gate dielectric layer disposed between the substrate and the gate, wherein the gate dielectric layer is in the shape of a barbell. The barbell has a thin center connecting to two bulging ends. Part of the bulging ends extends into the gate and the substrate.

Abstract: A display device includes a first scan line, a second scan line, a third scan line, a data line, a pixel, a low color-shifting circuit, and a black zone generation circuit. In the low color-shifting circuit, a low color-shifting switch receives a third scan signal from the third scan line to selectively couple a compensating capacitor to the second sub-pixel electrode. The black zone generation circuit receives a black zone generation signal to selectively couple either the first sub-pixel electrode or the second sub-pixel electrode to a common node such that either the first sub-pixel or the second sub-pixel becomes a black zone.

Abstract: A pixel electrode structure including a first electrode and a second electrode is provided. The first electrode has a first stripe electrode extended along a first direction and pleural first branch electrodes connected to the first strip electrode. The first branch electrodes include pleural first branch domain electrodes extended along a second direction and pleural second branch domain electrodes extended along a third direction substantially perpendicular to the second direction. The second electrode has a second stripe electrode extended along the first direction and pleural second branch electrodes connected to the second stripe electrode. The second branch electrodes include pleural third branch domain electrodes extended along the second direction and pleural fourth branch domain electrodes extended along the third direction. The first and the third branch domain electrodes are alternated to each other. The second and the fourth branch domain electrodes are alternated to each other.

Abstract: A power converter includes a rectifier and a power factor corrector. The rectifier is to be coupled to an alternating current power source and is configured to output a rectified signal. The power factor corrector includes a correcting circuit and a control circuit. The correcting circuit receives the rectified signal and is configured to generate an output voltage based on the rectified signal and a driving signal. The control circuit is configured to generate a first to-be-compared signal based on the rectified signal, to generate a second to-be-compared signal based on the output voltage, to compare the first and second to-be-compared signals, and to generate the driving signal based on a result of comparison performed thereby.

Abstract: A display panel is disclosed, comprising: a first electrode comprising a first trunk electrode and a second trunk electrode and a second electrode comprising a third trunk electrode and a fourth trunk electrode formed thereon, wherein when light passes through the display panel, the first and second trunk electrode respectively correspond to first and second dark lines crossing to each other to form a first cross site, the third and fourth trunk electrode respectively correspond to third and fourth dark lines crossing to each other to form a second cross site, the first and third dark lines respectively comprise first and second arc portions at the first and second cross sites near to a first scan line, and a first concave side of the first arc portion and the second concave side of the second arc portion face to sides opposite to each other.

Abstract: A backlight module includes a frame structure, a heat sink, a light source and a light guiding plate. The frame structure includes a cover unit that defines an airgap therein. The heat sink is located below the airgap of the cover unit. The light source directly contacts the heat sink. The light guiding plate is disposed to correspond in position to the light source for receiving light emitted from the light source. The heat sink is located between the light guiding plate and the cover unit.

Abstract: A method and a device for generating a three-dimensional image are provided. In the method, in an Nth time slot, an Nth left-eye image is received and stored in a download buffer of a first memory unit by a first control unit. An Nth right-eye image is received and stored in a download buffer of a second memory unit by a second control unit, where N is a positive integer from 1 to M, and M is a positive integer. In an (N+1)th time slot, the Nth right-eye image is received from the second control unit through a data transmission interface and stored in a receive buffer of the first memory unit. In an (N+2)th time slot, the Nth left-eye image and the Nth right-eye image are combined into an Nth three-dimensional image stored in a display buffer of the first memory unit for real time display.

Abstract: A display device is provided. The display device includes a pixel driving circuit including a liquid crystal capacitor coupled to a first node, a first storage capacitor, and a first voltage control unit. The first storage capacitor has a first terminal directly connected to a second node and a second terminal coupled to a common electrode. The first voltage control unit has first and second output terminals coupled to the first and second nodes, respectively. In a first period, the first voltage control unit feeds a first data voltage to the first node according to a first scan signal. In a second period later than the first period, the first voltage control unit feeds the first data voltage to the second node according to a second scan signal, such that a voltage level at the first node is changed to a first pixel voltage from the first data voltage.

Abstract: A computer implemented method for performing extraction is provided in the present invention. First, a layout of a semiconductor circuit having a resistor is imported by using a computer wherein a device region is defined in the layout and the resistor is located within the device region. Next, the device region of the layout are extracted, and a compensation value of Rs (Rc) is obtained according to the extracting step. An adjustment process is performed according to Rc to obtained a refined R value.

Abstract: A plant cultivation system including a main body, a cultivating dish, an environmental condition detecting unit, a control center module, and an actuation unit. The main body has an accommodating space. The cultivating dish is located in the accommodating space for cultivating a plant. The environmental condition detecting unit is located in the accommodating space for detecting an environment parameter in the accommodating space and correspondingly generating an environment parameter signal. The control center module includes a wireless transceiver module and a system chipset module. The wireless transceiver module is electrically connected to a monitoring device.

Abstract: A display panel is disclosed, which comprises: a first substrate with plural pixel units formed thereon, wherein the pixel units at least comprise a first subpixel unit being a blue pixel unit and a second subpixel unit being a green pixel unit, wherein the first subpixel unit comprises a first subpixel electrode comprising a first trunk electrode, and the second subpixel unit comprises a second subpixel electrode comprising a second trunk electrode; and a second substrate opposite to the first substrate. When light passes through the display panel, a width of a first dark line corresponding to the first trunk electrode is larger than that of a second dark line corresponding to the second trunk electrode.

Abstract: A computer implemented method for performing extraction is provided in the present invention. First, a layout of a semiconductor circuit having a resistor is imported by using a computer wherein a device region is defined in the layout and the resistor is located within the device region. Next, the device region of the layout are extracted, and a compensation value of Rs (Rc) is obtained according to the extracting step. An adjustment process is performed according to Rc to obtained a refined R value.

Abstract: A device comprises a substrate having at least one active region, an insulating layer above the substrate, and an electrode in a gate electrode layer above the insulating layer, forming a metal-oxide-semiconductor (MOS) capacitor. A first contact layer is provided on the electrode, having an elongated first pattern extending in a first direction parallel to the electrode. A contact structure contacts the substrate. The contact structure has an elongated second pattern extending parallel to the first pattern. A dielectric material is provided between the first and second patterns, so that the first and second patterns and dielectric material form a side-wall capacitor connected in parallel to the MOS capacitor.

Abstract: A display panel and a display device applying the same are provided. The display panel includes a first substrate, a second substrate, and a display medium disposed between the first substrate and the second substrate. The first substrate includes a first conductive layer having a first line width and a second conductive layer having a second line width smaller than the first line width. A first spacing is defined by a first sidewall of the second conductive layer and a second sidewall, located on the same side as the first sidewall, of the first conductive layer. A second spacing is defined by a third sidewall of the second conductive layer opposite to the first sidewall and a fourth sidewall, located on the same side as the third sidewall, of the first conductive layer. The first spacing is larger than the second spacing.

Abstract: An energy saving device for accelerated pressurization in an injection molding machine includes a mold needing vapor and cooled water or oil in an injection molding process. The cooled water or oil is provided by a pump, followed by connecting to the mold through a water or oil supply pipeline. The interior of the accelerated pressurization energy saving pipe is a through hole. Three or more spiral grooves are provided on the inner peripheral surface of the through hole and having an angle rotated in a front direction, with the lateral direction of each spiral groove having an inclined angle. The vapor or water or oil enforces angle rotation and inclined angle accelerated pressurization.

Abstract: A method for post-OPC verification including of several steps is provided. First, a pre-OPC layout of an integrated circuit (IC) is received. Then, a first OPC procedure is performed to obtain a post-OPC layout of the IC. After that, a first extraction process is performed on the pre-OPC layout and a second extraction process is performed on the post-OPC layout to respectively obtain a first netlist and a second netlist by using a processor. Next, a verification process is performed by using the processor to determine whether an electrical network of the first netlist and an electrical network of the second netlist are identical. The verification process is then terminated if the electrical network of the first netlist and the electrical network of the second netlist are identical. An apparatus for post-OPC verification is also provided.

Abstract: A semiconductor structure includes a substrate and a metal gate. The metal gate includes a metallic filling layer and disposed over the substrate. The semiconductor structure further includes a dielectric material over the metallic filling layer and separating the metallic filling layer from a conductive trace. The conductive trace is over the dielectric material. The semiconductor structure further includes a conductive plug extending longitudinally through the dielectric material and ending with a lateral encroachment inside the metallic filling layer along a direction. The lateral direction is substantially perpendicular to the longitudinal direction of the conductive plug.