Abstract: The present application discloses a method of fabricating a display apparatus, comprising providing a carrier substrate comprising a base substrate and an adhesive layer over the base substrate, wherein the base substrate comprises a plurality of fluid passages between the base substrate and the adhesive layer, and a plurality of fluid inlets connected with the plurality of fluid passages; forming a product substrate on a side of the adhesive layer distal to the base substrate; dispensing a detaching agent through the plurality of fluid inlets to the plurality of fluid passages, and contacting the detaching agent with the adhesive layer through the plurality of fluid passages; and detaching the product substrate from the carrier substrate.

Abstract: A chip package is provided. The chip package includes a substrate having conductive pads therein and adjacent to a first surface thereof. Chips are attached on a second surface opposite to the first surface of the substrate, and an encapsulation layer covers the chips. First redistribution layers are disposed between the second surface of the substrate and the encapsulation layer, and second redistribution layers are disposed on the encapsulation layer. First conductive structures and second conductive structures are disposed in the encapsulation layer. Each of first and second conductive structures respectively includes at least one bonding ball. The first conductive structures are configured to connect first and second redistribution layers, and the second conductive structures are configured to connect the second redistribution layers and the chip. A method of forming the chip package is also provided.

Abstract: A keyboard includes a base plate, a pressure sensing layer, plural key structures, a circuit board, a flexible layer and a controlling unit. The pressure sensing layer is disposed on the base plate and located under the circuit board. The flexible layer is disposed on the pressure sensing layer and located under the circuit board. While a key structure is depressed, a part of the key structure is penetrated through the circuit board to press the flexible layer, and a force is transmitted from the flexible layer to the pressure sensing layer. The controlling unit compares the force with a predetermined force value. According to the comparing result, the controlling unit generates a corresponding pressure sensing signal. Consequently, the use of a single key structure can achieve the functions of multiple keys.

Abstract: A keyboard includes a base plate, a pressure sensing layer, plural key structures, a circuit board, a flexible layer and a controlling unit. The pressure sensing layer is disposed on the base plate and located under the circuit board. The flexible layer is disposed on the pressure sensing layer and located under the circuit board. While a key structure is depressed, a part of the key structure is penetrated through the circuit board to press the flexible layer, and a force is transmitted from the flexible layer to the pressure sensing layer. The controlling unit compares the force with a predetermined force value. According to the comparing result, the controlling unit generates a corresponding pressure sensing signal. Consequently, the use of a single key structure can achieve the functions of multiple keys.

Abstract: A key structure includes a pedestal with a sliding groove, an upper cover, a triggering element, and a spring strip. The spring strip is movable within the sliding groove. The triggering element is arranged between the pedestal and the upper cover, and located beside the spring strip. When a keycap of the key structure is depressed, the triggering element is moved relative to the pedestal to push the spring strip. In response to the elasticity of the pushed spring strip, the spring strip is slid within the sliding groove to collide with the upper cover. Consequently, the key structure generates sound surely.

Abstract: A key structure includes a circuit board, a housing, a first metallic element, a second metallic element, a keycap and a conductive strip. The conductive strip is disposed within the housing. The first metallic element and the second metallic element are electrically connected with the circuit board. The housing is disposed on the circuit board. The keycap is fixed on the housing. While the keycap is depressed, a first end of the conductive strip is pressed by the triggering part and the conductive strip is swung relative to the housing. Moreover, a second end of the conductive strip collides with the second metallic element. Consequently, the key structure is triggered. When the second end of the conductive strip collides with the second metallic element, a click sound is generated.

Abstract: A chip package is provided. The chip package includes a sensing device. The chip package also includes a first conductive structure disposed on the sensing device and electrically connected to the sensing device. The chip package further includes a chip and a second conductive structure disposed on the sensing device. The chip includes an integrated circuit device. The second conductive structure is positioned on the chip and is electrically connected to the integrated circuit device and the first conductive structure. In addition, the chip package includes an insulating layer covering the sensing device and the chip. The insulating layer has a hole. The first conductive structure is positioned under the bottom of the hole. The top surface of the insulating layer is coplanar with the top surface of the second conductive structure. A method for forming the chip package is also provided.

Abstract: The present disclosure provides a method for forming an active layer with a pattern. The method includes forming an amorphous silicon layer and forming a function layer on the amorphous silicon layer. The function layer has a same pattern as the active layer. The method further includes performing a crystallization process for converting the amorphous silicon layer to a poly-silicon layer. The poly-silicon layer has first portions covered by the function layer and second portions not covered by the function layer, and grain sizes of the poly-silicon in the first portions are larger than grain sizes of the poly-silicon in the second portions.

Abstract: A scissors-type connecting member includes a first frame and a second frame. The first frame includes a rotating shaft. The second frame includes a pivot hole, an entrance and a stopper. After the rotating shaft is introduced into the pivot hole through the entrance, the first frame is pivotally coupled to the second frame. The stopper is located near the entrance or arranged between the entrance and the pivot hole. A position of the rotating shaft is limited between the stopper and the pivotal hole by the stopper. Consequently, the scissors-type connecting member is assembled easily, and the stability of connecting a first frame and a second frame of the scissors-type connecting member is enhanced. Moreover, the present invention also provides a key structure with the scissors-type connecting member.

Abstract: A chip package includes a chip, a laser stop layer, a first through hole, an isolation layer, a second through hole and a conductive layer. The laser stop layer is disposed above a first surface of the chip, and the first through hole is extended from a second surface to the first surface of the chip to expose the laser stop layer. The isolation layer is below the second surface and in the first through hole, and the isolation layer has a third surface opposite to the second surface. The second through hole is extended from the third surface to the first surface, and the second through hole is through the first through hole to expose the laser stop layer. The conductive layer is disposed below the third surface and extended into the second through hole to contact the laser stop layer.

Abstract: An array substrate, a manufacturing method thereof, a display device, a thin-film transistor (TFT) and a manufacturing method thereof are disclosed. The method for manufacturing the TFT comprises: forming a pattern of an active layer and a gate insulating layer provided with a metal film on a base substrate; patterning the metal film by one patterning process, and forming patterns of a gate electrode, a source electrode, a drain electrode, a gate line and a data line; forming a passivation layer on the base substrate; patterning the passivation layer by one patterning process, and forming a source contact hole, a drain contact hole and a bridge structure contact hole; and forming a transparent conductive film on the base substrate, and removing partial transparent conductive film to form a source contact portion, a drain contact portion (214), a pixel electrode and a bridge structure. The manufacturing method can reduce the number of the patterning processes.

Abstract: A chip module is provided. The chip module includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a signal pad region adjacent to the upper surface. A recess extends from the upper surface toward the lower surface along the sidewall of the chip. A redistribution layer is electrically connected to the signal pad region and extends into the recess. A circuit board is located between the upper surface and the lower surface and extends into the recess. A conducting structure is located in the recess and electrically connects the circuit board to the redistribution layer. A method for forming the chip module is also provided.

Abstract: A key structure includes a pedestal with a sliding groove, an upper cover, a triggering element, and a spring strip. The spring strip is movable within the sliding groove. The triggering element is arranged between the pedestal and the upper cover, and located beside the spring strip. When a keycap of the key structure is depressed, the triggering element is moved relative to the pedestal to push the spring strip. In response to the elasticity of the pushed spring strip, the spring strip is slid within the sliding groove to collide with the upper cover. Consequently, the key structure generates sound surely.

Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.

Abstract: A chip package includes a chip, a dam layer, a permanent adhesive layer, a support, a buffer layer, a redistribution layer, a passivation layer, and a conducting structure. A conducting pad and a sensing device of the chip are located on a first surface of a substrate of the chip, and the conducting pad protrudes from the side surface of the substrate. The dam layer surrounds the sensing device. The permanent adhesive layer is between the support and the substrate. The support and the permanent adhesive layer have a trench to expose the conducting pad. The buffer layer is located on the support. The redistribution layer is located on the buffer layer and on the support, the permanent adhesive layer, and the conducting pad facing the trench. The passivation layer covers the redistribution layer, the buffer layer, and the conducting pad.

Abstract: An integrated circuit comprises a memory array including diffusion bit lines having composite impurity profiles in a substrate. A plurality of word lines overlies channel regions in the substrate between the diffusion bit lines, with data storage structures such as floating gate structures or dielectric charge trapping structures, at the cross-points. The composite impurity diffusion bit lines provide source/drain terminals on opposing sides of the channel regions that have high conductivity, good depth and steep doping profiles, even with channel region critical dimensions below 50 nanometers.

Abstract: The invention provides an electronic device package and fabrication method thereof. The electronic device package includes a sensor chip. An upper surface of the sensor chip comprises a sensing film. A covering plate having an opening structure covers the upper surface of the sensor chip. A cavity is between the covering plate and the sensor chip, corresponding to a position of the sensing film, where the cavity communicates with the opening structure. A spacer is between the covering plate and the sensor chip, surrounding the cavity. A pressure releasing region is between the spacer and the sensing film.

Abstract: Embodiments of the present invention provide a method of processing a surface of a polysilicon and a method of processing a surface of a substrate assembly. The method of processing a surface of a polysilicon includes forming a material film on the surface of the polysilicon; and processing, by using a chemico-mechanical polishing technology, the surface of the polysilicon on which the material film is formed. The material film is selected such that the polysilicon is preferentially removed in a polishing process.

Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.

Abstract: A chip package including a first device substrate is provided. The first device substrate is attached to a first surface of a second device substrate. A third device substrate is attached to a second surface of the second device substrate opposite to the first surface. An insulating layer covers the first, second and third device substrates and has at least one opening therein. At least one bump is disposed under a bottom of the opening. A redistribution layer is disposed on the insulating layer and electrically connected to the bump through the opening. A method for forming the chip package is also provided.