Abstract: A chip package including a first substrate is provided. The first substrate includes a sensing device. A second substrate is attached onto the first substrate and includes an integrated circuit device. A first conductive structure is electrically connected to the sensing device and the integrated circuit device through a redistribution layer disposed on the first substrate. An insulating layer covers the first substrate, the second substrate and the redistribution layer. The insulating layer has a hole therein and a second conductive structure is disposed under the bottom of the hole. A method for forming the chip package is also provided.

Abstract: The invention provides an electronic device package and fabrication method thereof. The electronic device package includes a sensor chip. An upper surface of the sensor chip comprises a sensing film. A covering plate having an opening structure covers the upper surface of the sensor chip. A cavity is between the covering plate and the sensor chip, corresponding to a position of the sensing film, where the cavity communicates with the opening structure. A spacer is between the covering plate and the sensor chip, surrounding the cavity. A pressure releasing region is between the spacer and the sensing film.

Abstract: A chip package including a first substrate having a first surface and a second surface opposite thereto is provided. The first substrate has a micro-electric element and a plurality of conducting pads adjacent to the first surface. The first substrate has a plurality of openings respectively exposing a portion of each conducting pad. A second substrate is disposed on the first surface. An encapsulation layer is disposed on the first surface and covers the second substrate. A redistribution layer is disposed on the second surface and extends into the openings to electrically connect the conducting pads.

Abstract: A chip package includes a semiconductor chip, a first chip, a first connection portion, a molding layer, a metal redistribution layer and a packaging layer. The semiconductor chip includes a first conductive pad and a second conductive pad disposed on an upper surface of the semiconductor chip. The first chip is disposed on the upper surface, and the first chip has at least a first chip conductive pad. The first connection portion directly electrically connects the first chip conductive pad and the first conductive pad. The molding layer covers the upper surface, the first chip and the first connection portion, and the molding layer is formed with an opening exposing a second conductive pad. The metal redistribution layer is disposed in the opening, electrically connected to the second conductive pad and extending to the molding layer. The packaging layer covers the metal redistribution layer and the molding layer.

Abstract: A magnetic element includes a first magnetic core, a second magnetic core, an intermediate magnetic core, a first winding coil, and a second winding coil. The intermediate magnetic core is arranged between the first magnetic core and the second magnetic core. After the first magnetic core and the intermediate magnetic core are coupled with each other, a first winding space and a first air gap are defined. After the second magnetic core and the intermediate magnetic core are coupled with each other, a second winding space and a second air gap are defined. The first winding coil is disposed within the first winding space and arranged around the first air gap. The second winding coil is disposed within the second winding space and arranged around the second air gap. The first winding coil and the second winding coil are connected with each other in series.

Abstract: A USB testing device is provided for an electronic device having a USB port. The USB testing device includes a first USB control unit, a second USB control unit, and a micro-processor. When the first USB control unit has received power, the first USB control unit processes a connection test via a first data port. When the second USB control unit has received the power, the second USB control unit processes a connection test via a second data port. When the USB testing device is connected to the USB port, the micro-processor provides power to the first USB control unit. When the first USB control unit receives power, the first USB control unit provides power to the second USB control unit after waiting for a predetermined period of time. The electronic device determines whether the first and second data ports are operating properly.

Abstract: A chip package is provided. The chip package includes a substrate having a first surface and a second surface opposite thereto. The substrate includes a sensing device and a conducting pad therein. The sensing device and the conducting pad are adjacent to the first surface. The conducting pad has a sidewall laterally protruding from a sidewall of the substrate. An encapsulation layer is attached to the first surface of the substrate to cover the sensing device and the conducting pad. A redistribution layer is disposed on the second surface of the substrate and extends to contact the sidewall of the conducting pad. An end of the redistribution layer protrudes from the first surface of the substrate and is level with a third surface of the encapsulation layer that is opposite to the first surface. A method of forming the chip package is also provided.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A carrier and a dam element are provided, and the dam element is adhered to the carrier by a temporary bonding layer. The dam element is bonded on the wafer. A first isolation layer, a redistribution layer, a second isolation layer, and a conductive structure are formed on the wafer in sequence. The carrier, the dam element and the wafer are diced to form a semiconductor element. The semiconductor element is disposed on a printed circuit board, such that the conductive structure is electrically connected to the printed circuit board. An adhesion force of the temporary bonding layer is eliminated to remove the carrier. A lens assembly is disposed on the printed circuit board, such that the semiconductor element without the carrier is located in the lens assembly.

Abstract: An integrated circuit comprises a memory array including diffusion bit lines having composite impurity profiles in a substrate. A plurality of word lines overlies channel regions in the substrate between the diffusion bit lines, with data storage structures such as floating gate structures or dielectric charge trapping structures, at the cross-points. The composite impurity diffusion bit lines provide source/drain terminals on opposing sides of the channel regions that have high conductivity, good depth and steep doping profiles, even with channel region critical dimensions below 50 nanometers.

Abstract: A semiconductor package includes a semiconductor chip, a first and a second depression, a first and second redistribution layer and a packaging layer. The semiconductor chip has an electronic component and a conductive pad that are electrically connected and disposed on an upper surface of the semiconductor chip. The first depression and first redistribution layer extend from the upper surface toward the lower surface of the semiconductor chip. The first redistribution layer and the conductive pad are electrically connected. The second depression and the second redistribution layer extends from the lower surface toward the upper surface and is in connection with the first depression through a connection portion. The second redistribution layer is electrically connected to the first redistribution layer through the connection portion. The packaging layer is disposed on the lower surface.

Abstract: A chip package includes a semiconductor chip, insulation layer, redistribution layer and packaging layer and is formed with a cavity. The semiconductor chip has an electronic component and a conductive pad. The conductive pad and the electronic component are disposed on an upper surface of the semiconductor chip and electrically connected. The cavity opens from a lower surface of the semiconductor chip and tapers toward the upper surface to expose the conductive pad. The insulation layer coats the lower surface and a portion of the cavity. The insulation layer is formed with a gap to expose the conductive pad. The redistribution layer coats the lower surface and a portion of the cavity and is electrically connected to the conductive pad through the gap. The packaging layer coats the lower surface and a portion of the cavity.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A temporary bonding layer is used to adhere a carrier to a first surface of a wafer. A redistribution layer, an insulating layer, and a conductive structure are formed on a second surface of the wafer opposite to the first surface, such that a semiconductor element is formed. The semiconductor element is diced from the insulating layer to the carrier, such that the semiconductor element forms at least one sub-semiconductor element. UV light is used to irradiate the sub-semiconductor element, such that adhesion of the temporary bonding layer is eliminated. The carrier of the sub-semiconductor element is removed.

Abstract: A power module includes a substrate; a conductive path layer formed on the substrate with a specific pattern as an inductor; a connection layer being formed on the substrate and electrically connected to a first terminal of the inductor; and a first transistor, electrically mounted on the substrate through the connection layer.

Abstract: An electronic device is provided. When the electronic device is at a power exhaustion state and a first external device with a charging function is coupled to a connection interface to provide a first supply voltage to a power pin of the connection interface, a voltage regulation unit transforms the first supply voltage to a first operation voltage, and a storage unit powered by the first operation voltage outputs device information of the electronic device to the first external device through a signal transmitting/receiving pin set of the connection interface. When the first external device provides a second supply voltage to the power pin in response to the device information, the electronic device enters a charging mode. In the charging mode, the charging unit provides a charging voltage according to the second supply voltage to charge the battery unit and provides a second operation voltage to a processing unit.

Abstract: A chip package including a first substrate is provided. A plurality of first conductive pads is disposed on a first side of the first substrate. A second substrate is attached onto a second side opposite to the first side of the first substrate. The second substrate includes a micro-electric element and has a plurality of second conductive pads corresponding to the plurality of first conductive pads, disposed on a first side of the second substrate and between the first substrate and the second substrate. A redistribution layer is disposed on a second side opposite to the first side of the second substrate. The redistribution layer penetrates the second substrate, second conductive pads and the first substrate and extends into the first conductive pads to electrically connect the first and second conductive pads.

Abstract: A chip package including a first substrate having a first surface and a second surface opposite thereto is provided. The first substrate has a micro-electric element and a plurality of conducting pads adjacent to the first surface. The first substrate has a plurality of openings respectively exposing a portion of each conducting pad. A second substrate is disposed on the first surface. An encapsulation layer is disposed on the first surface and covers the second substrate. A redistribution layer is disposed on the second surface and extends into the openings to electrically connect the conducting pads.

Abstract: An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed on the first substrate, wherein the second substrate has at least one opening penetrating through the second substrate, and the at least one opening defines a plurality of conducting regions electrically insulated from each other in the second substrate; a first insulating layer disposed on a side of the first substrate and filling in the at least one opening of the second substrate; a carrier substrate disposed on the second substrate; a second insulating layer disposed on a surface and a sidewall of the carrier substrate; and a conducting layer disposed on the second insulating layer on the carrier substrate and electrically contacting with one of the conducting regions.

Abstract: A chip package structure and a method for forming the chip package structure are disclosed. At least a block is formed on a surface of a cover, the cover is mounted on a substrate having a sensing device formed thereon for covering the sensing device, and the block is disposed between the cover and the sensing device. In the present invention, the block is mounted on the cover, there is no need to etch the cover to form a protruding portion, and thus the method of the present invention is simple and has low cost.

Abstract: A method for forming a chip package includes: providing a substrate having a first and a second surfaces; removing a portion of the substrate to form openings in the substrate, wherein the openings extend from the first surface towards the second surface or from the second surface towards the first surface; after forming the openings, at least a first portion of the substrate serves as a first movable bulk, and at least a second portion of the substrate serves as a second movable bulk, wherein the first movable bulk and the second movable bulk are respectively located between the openings; disposing a protecting substrate on the second surface of the substrate; forming a through-hole in the protecting substrate; and forming a conducting layer on the protecting substrate, wherein the conducting layer extends from a surface of the protecting substrate into the through-hole to electrically connect the second movable bulk.

Abstract: A magnetic core includes an ellipse-shaped central post and two side posts. The ellipse-shaped central post includes a long axis and a short axis. The length of the long axis is greater than the length of the short axis. The two side posts are disposed on two sides of the ellipse-shaped central post and opposite to each other. The two side posts are connected with the ellipse-shaped central post through two connecting portions respectively for defining at least one winding space with the ellipse-shaped central post. By utilizing the ellipse-shaped central post, the volume of the winding space is increased, the diameter of the wire of the winding coil can be increased, the temperature of the winding encapsulation is easy to be lowered, the over-volume issue of the winding encapsulation is avoided, and the safe distance between the bobbin and the winding encapsulation is increased, so that the present disclosure meets the safety regulation.