Patents by Inventor Chien-Hung Liu

Chien-Hung Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170005115
    Abstract: The present disclosure provides a method for forming an active layer with a pattern. The method includes forming an amorphous silicon layer and forming a function layer on the amorphous silicon layer. The function layer has a same pattern as the active layer. The method further includes performing a crystallization process for converting the amorphous silicon layer to a poly-silicon layer. The poly-silicon layer has first portions covered by the function layer and second portions not covered by the function layer, and grain sizes of the poly-silicon in the first portions are larger than grain sizes of the poly-silicon in the second portions.
    Type: Application
    Filed: August 14, 2015
    Publication date: January 5, 2017
    Inventors: ZUQIANG WANG, CHIEN HUNG LIU, YU CHENG CHAN, LUJIANG HUANGFU
  • Publication number: 20160372445
    Abstract: A chip package is provided. The chip package includes a substrate having conductive pads therein and adjacent to a first surface thereof. Chips are attached on a second surface opposite to the first surface of the substrate, and an encapsulation layer covers the chips. First redistribution layers are disposed between the second surface of the substrate and the encapsulation layer, and second redistribution layers are disposed on the encapsulation layer. First conductive structures and second conductive structures are disposed in the encapsulation layer. Each of first and second conductive structures respectively includes at least one bonding ball. The first conductive structures are configured to connect first and second redistribution layers, and the second conductive structures are configured to connect the second redistribution layers and the chip. A method of forming the chip package is also provided.
    Type: Application
    Filed: May 25, 2016
    Publication date: December 22, 2016
    Inventors: Ho-Yin YIU, Ying-Nan WEN, Chien-Hung LIU, Wei-Chung YANG
  • Publication number: 20160322305
    Abstract: A chip package includes a chip, a laser stop layer, a first though hole, an isolation layer, a second though hole and a conductive layer. The laser stop layer is disposed above a first surface of the chip, and the first though hole is extended from a second surface to the first surface of the chip to expose the laser stop layer. The isolation layer is below the second surface and in the first through hole, and the isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the first surface, and the second though hole is through the first through hole to expose the laser stop layer. The conductive layer is disposed below the third surface and extended into the second though hole to contact the laser stop layer.
    Type: Application
    Filed: April 26, 2016
    Publication date: November 3, 2016
    Inventors: Shih-Yi LEE, Ying-Nan WEN, Chien-Hung LIU, Ho-Yin YIU
  • Publication number: 20160307978
    Abstract: A manufacturing method of an array substrate, an array substrate and a display device are provided. The manufacturing method of the array substrate comprises: forming a first conductive thin film (100) on a base substrate (1); and patterning the first conductive thin film (100), to form a pattern of a cathode (11) on a first region (11) of the base substrate (1), and form a pattern of a gate electrode (4) on a second region (12) of the base substrate (1). Complexity and process time of a fabrication process of an array substrate can be reduced, a fabrication process of an organic electroluminescent panel can be simplified, and production cost can be reduced, by forming a cathode layer of a light-emitting diode and a gate electrode layer of a thin film transistor in different regions of the base substrate at the same time by one patterning process.
    Type: Application
    Filed: March 12, 2015
    Publication date: October 20, 2016
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zheng LIU, Xiaoyong LU, Xiaolong LI, Chien Hung LIU, Chunping LONG
  • Publication number: 20160300866
    Abstract: An array substrate, a manufacturing method thereof, a display device, a thin-film transistor (TFT) and a manufacturing method thereof are disclosed. The method for manufacturing the TFT comprises: forming a pattern of an active layer and a gate insulating layer provided with a metal film on a base substrate patterning the metal film by one patterning process, and forming patterns of a gate electrode, a source electrode, a drain electrode, a gate line and a data line; forming a passivation layer on the base substrate; patterning the passivation layer by one patterning process, and forming a source contact hole, a drain contact hole and a bridge structure contact hole; and forming a transparent conductive film on the base substrate, and removing partial transparent conductive film to form a source contact portion, a drain contact portion, a pixel electrode and a bridge structure.
    Type: Application
    Filed: September 20, 2014
    Publication date: October 13, 2016
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chunping LONG, Jang Soon IM, Chien Hung LIU
  • Patent number: 9455007
    Abstract: A memory device includes a memory array having a plurality of rows and columns of array blocks disposed in array block areas, array blocks including sub-arrays of memory cells arranged in rows and columns with word lines disposed in a patterned gate layer along the rows and one or more patterned conductor layers including bit lines disposed along the columns. A plurality of sets of local word line drivers is arranged in rows and columns disposed adjacent to corresponding array blocks. A set of global word line drivers driving global word lines disposed in an overlying patterned conductor layer over the one or more patterned conductor layers in the array blocks.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: September 27, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Tsung Lin, Chien-Hung Liu, Jyun-Siang Huang
  • Publication number: 20160254287
    Abstract: A thin-film transistor (TFT), a manufacturing method thereof, display substrate and a display device are disclosed. The TFT includes: an active layer, gate insulating layer, gate electrode, an interlayer dielectric layer, source electrode and a drain electrode disposed on a base substrate in sequence. The source electrode and drain electrode are respectively connected with the active layer via a through hole exposing the active layer; the gate insulating layer at least includes a silicon oxide layer and a silicon nitride layer in a two-layer structure; the interlayer dielectric layer at least includes silicon oxide layers and silicon nitride layers in a four-layer structure; the silicon oxide layers and silicon nitride layers of the gate insulating layer and the interlayer dielectric layer are alternately arranged; and the dimension of one side of the through hole away from the base substrate is greater than that of one side close to the base substrate.
    Type: Application
    Filed: December 29, 2014
    Publication date: September 1, 2016
    Inventors: Zuqiang WANG, Chien Hung LIU
  • Patent number: 9422042
    Abstract: A cantilevered rotatable carcass carrier includes a main carcass and two secondary carcasses. The two secondary carcasses are pivotally connected to two sides of the main carcass through two first cantilevers. The secondary carcasses are further pivotally connected with second cantilevers. The secondary carcasses further pivotally connected with an airtight cabin through the second cantilevers. By turning the secondary carcasses, the airtight cabin can be located under the main carcass to form a submarine mode or located above the main carcass to form a watch mode, broadening the recreation space on the water, such that the recreation space on the water is not limited to the type of two-dimensional space on the water. The present invention provides a novel water recreational carrier for the demands of different situations.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: August 23, 2016
    Assignee: SHIP AND OCEAN INDUSTRIES R&D CENTER
    Inventors: Min-Tsung Chen, Tsai-Min Chiang, Chien-Hung Liu, Po-Feng Wang
  • Patent number: 9424979
    Abstract: A magnetic element includes a first magnetic core, a second magnetic core, an intermediate magnetic core, a first winding coil, and a second winding coil. The intermediate magnetic core is arranged between the first magnetic core and the second magnetic core. After the first magnetic core and the intermediate magnetic core are coupled with each other, a first winding space and a first air gap are defined. After the second magnetic core and the intermediate magnetic core are coupled with each other, a second winding space and a second air gap are defined. The first winding coil is disposed within the first winding space and arranged around the first air gap. The second winding coil is disposed within the second winding space and arranged around the second air gap. The first winding coil and the second winding coil are connected with each other in series.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: August 23, 2016
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Han-Hsing Lin, Chien-Hung Liu, Yu-Liang Hung, Kun-Te Chen, Yi-Lin Chen, Fan-Lin Liu
  • Publication number: 20160229687
    Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.
    Type: Application
    Filed: January 27, 2016
    Publication date: August 11, 2016
    Inventors: Ying-Nan WEN, Ho-Yin YIU, Chien-Hung LIU
  • Publication number: 20160233260
    Abstract: An embodiment of the invention provides a chip package which includes a first substrate including a device region and having a first surface and a second surface opposite thereto. A dielectric layer is disposed on the second surface of the first substrate and includes a conducting pad structure connected to the device region, and the first substrate completely covers the conducting pad structure. A second substrate is disposed on the second surface of the first substrate and the dielectric layer is located between the first substrate and the second substrate. The second substrate has a first opening exposing a surface of the conducting pad structure, and a redistribution layer is conformally disposed on a sidewall of the first opening and the surface of the exposed conducting pad structure. A method for forming the chip package is also provided.
    Type: Application
    Filed: February 2, 2016
    Publication date: August 11, 2016
    Inventors: Ho-Yin YIU, Ying-Nan WEN, Chien-Hung LIU
  • Patent number: 9406578
    Abstract: A semiconductor package includes a semiconductor chip, a first and a second depression, a first and second redistribution layer and a packaging layer. The semiconductor chip has an electronic component and a conductive pad that are electrically connected and disposed on an upper surface of the semiconductor chip. The first depression and first redistribution layer extend from the upper surface toward the lower surface of the semiconductor chip. The first redistribution layer and the conductive pad are electrically connected. The second depression and the second redistribution layer extends from the lower surface toward the upper surface and is in connection with the first depression through a connection portion. The second redistribution layer is electrically connected to the first redistribution layer through the connection portion. The packaging layer is disposed on the lower surface.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: August 2, 2016
    Assignee: XINTEC INC.
    Inventors: Ying-Nan Wen, Chien-Hung Liu, Ho-Yin Yiu
  • Publication number: 20160218124
    Abstract: The embodiments of the present invention provide a thin film transistor driving backplane and a manufacturing method thereof, and a display panel. The manufacturing method may comprise: manufacturing a backplane base disposed with a plurality of active device structures; disposing an electrode layer on the backplane base; and manufacturing the electrode layer into a source electrode, a drain electrode and a pixel electrode integrally disposed with the drain electrode by one patterning process.
    Type: Application
    Filed: December 12, 2013
    Publication date: July 28, 2016
    Inventors: ZUQIANG WANG, CHIEN HUNG LIU
  • Publication number: 20160211233
    Abstract: A chip module is provided. The chip module includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a signal pad region adjacent to the upper surface. A recess extends from the upper surface toward the lower surface along the sidewall of the chip. A redistribution layer is electrically connected to the signal pad region and extends into the recess. A circuit board is located between the upper surface and the lower surface and extends into the recess. A conducting structure is located in the recess and electrically connects the circuit board to the redistribution layer. A method for forming the chip module is also provided.
    Type: Application
    Filed: January 13, 2016
    Publication date: July 21, 2016
    Inventors: Ho-Yin YIU, Ying-Nan WEN, Chien-Hung LIU
  • Patent number: 9397138
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. A carrier and a dam element are provided, and the dam element is adhered to the carrier by a temporary bonding layer. The dam element is bonded on the wafer. A first isolation layer, a redistribution layer, a second isolation layer, and a conductive structure are formed on the wafer in sequence. The carrier, the dam element and the wafer are diced to form a semiconductor element. The semiconductor element is disposed on a printed circuit board, such that the conductive structure is electrically connected to the printed circuit board. An adhesion force of the temporary bonding layer is eliminated to remove the carrier. A lens assembly is disposed on the printed circuit board, such that the semiconductor element without the carrier is located in the lens assembly.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: July 19, 2016
    Assignee: XINTEC INC.
    Inventor: Chien-Hung Liu
  • Publication number: 20160204061
    Abstract: A chip package including a chip, a first though hole, a conductive structure, a first isolation layer, a second though hole and a first conductive layer. The first though hole is extended from a second surface to a first surface to expose a conductive pad, and the conductive structure is on the second surface and extended to the first though hole to contact the conductive pad. The conductive structure includes a second conductive layer and a laser stopper. The first isolation layer is on the second surface and covering the conductive structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stopper, and the first conductive layer is on the third surface and extended to the second though hole to contact the laser stopper.
    Type: Application
    Filed: January 11, 2016
    Publication date: July 14, 2016
    Inventors: Ho-Yin YIU, Ying-Nan WEN, Chien-Hung LIU, Shih-Yi LEE
  • Publication number: 20160190063
    Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.
    Type: Application
    Filed: December 29, 2015
    Publication date: June 30, 2016
    Inventors: Ying-Nan WEN, Chien-Hung LIU, Shih-Yi LEE, Ho-Yin YIU
  • Publication number: 20160192094
    Abstract: A device for playing music includes a maglev unit and a base unit. The maglev unit outputs a first sound signal based on a physical signal corresponding to an original sound signal. The base unit provides the physical signal to the maglev unit via a first wireless transmission, and outputs a second sound signal based on the original sound signal. The base unit includes a maglev control module, a power supply module and a processor. The maglev control module generates a magnetic force according to a first current to make the maglev unit float on the base unit. When the first current is continuously within a predetermined current range for a predetermined time duration, the processor controls the power supply module to output the first current, and to supply an electrical energy to the maglev unit via a second wireless transmission that is different from the first wireless transmission.
    Type: Application
    Filed: March 26, 2015
    Publication date: June 30, 2016
    Applicant: Quanta Computer Inc.
    Inventor: Chien-Hung LIU
  • Patent number: 9376181
    Abstract: A water craft able to offer fast rescue includes a water craft provided with a pressurization pump and a high pressure air reservoir to have air pressurized and poured into the high pressure air reservoir and stored therein. The water craft is formed with a concealed storage space having an uninflated rescue device received therein. The rescue device communicates with the high pressure air reservoir so that the rescue device can be inflated via the high pressure air reservoir. Thus, before inflated, the rescue device can be entirely received in the concealed storage space, letting the water craft have good maneuverability and, after inflated, the rescue device will be ejected out of the concealed storage space for carrying many persons thereon, thus advantageous to carry out rescue mission.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: June 28, 2016
    Assignee: SHIP AND OCEAN INDUSTRIES R&D CENTER
    Inventors: Tsai-Min Chiang, Chien-Hung Liu, Fan-Bin Tseng, Jung Liao
  • Patent number: 9379072
    Abstract: A chip package including a first substrate is provided. A plurality of first conductive pads is disposed on a first side of the first substrate. A second substrate is attached onto a second side opposite to the first side of the first substrate. The second substrate includes a micro-electric element and has a plurality of second conductive pads corresponding to the plurality of first conductive pads, disposed on a first side of the second substrate and between the first substrate and the second substrate. A redistribution layer is disposed on a second side opposite to the first side of the second substrate. The redistribution layer penetrates the second substrate, second conductive pads and the first substrate and extends into the first conductive pads to electrically connect the first and second conductive pads.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: June 28, 2016
    Assignee: XINTEC INC.
    Inventors: Chien-Hung Liu, Ying-Nan Wen