Abstract: A silicon based substrate includes a silicon wafer, a first circuit substrate and a second circuit substrate. The silicon wafer includes a first surface and a second surface and at least a through silicon via. The first circuit substrate is disposed on the first surface and includes a plurality of first dielectric layers and a plurality of first conductive trace layers alternately stacked. The second circuit substrate is disposed on the second surface and includes a plurality of second dielectric layers and a plurality of second conductive trace layers alternately stacked. The trace density of the first conductive trace layers is higher than the trace density of the second conductive trace layers. Otherwise, the first dielectric layer includes an inorganic material and the second dielectric layer includes an organic material. A manufacturing method of the silicon based substrate is also provided.

Abstract: A semiconductor device with a TSV and a shelter is provided. The semiconductor device includes a substrate, a circuit area, at least a TSV and a shelter. The circuit area and the TSV are disposed on the substrate, and the TSV penetrates through the substrate. The shelter is disposed on the substrate and at least one part thereof is between the circuit area and the TSV in order to shelter EMI between the TSV and the circuit area. The novel structure prevents the circuits in the circuit area being affected by noise caused by TSV when TSV acts as a power pin.

Abstract: A method for fabricating through-silicon via structure includes the steps of: providing a semiconductor substrate; forming at least one semiconductor device on surface of the semiconductor substrate; forming a dielectric layer on the semiconductor device, in which the dielectric layer includes at least one via hole; forming a first conductive layer on the dielectric layer and filling the via hole; performing an etching process to form a through-silicon via in the first conductive layer, the dielectric layer, and the semiconductor substrate; depositing a second conductive layer in the through-silicon via and partially on the first conductive layer; and planarizing a portion of the second conductive layer until reaching the surface of the first conductive layer.

Abstract: A method for predicting tolerable contact-to-gate spacing is provided. At first, a wafer with a plurality of source/drain contacts are provided. Then, a plurality of testing gate lines are formed on the wafer by using a photomask. In one die, there are different contact-to-gate distances ranging from d+?d to d??d wherein d is the standard spacing and ?d<d. Then, the wafer is inspected to find failure counts corresponding to each contact-to-gate distance. The tolerable spacing is determined according to the failure counts and the contact-to-gate distances based on a statistical method.

Abstract: A through-silicon via structure includes a substrate with a first side and a second side, a through-silicon hole connecting the first side and the second side and filled with a conductive material, a passivation layer disposed on and contacting the first side and covering the through-silicon hole, and a protection ring surrounding but not contacting the through-silicon hole and exposed by the first side and the second side. The protection ring is filled with an insulating material.

Abstract: A silicon based substrate includes a silicon wafer, a first circuit substrate and a second circuit substrate. The silicon wafer includes a first surface and a second surface and at least a through silicon via. The first circuit substrate is disposed on the first surface and includes a plurality of first dielectric layers and a plurality of first conductive trace layers alternately stacked. The second circuit substrate is disposed on the second surface and includes a plurality of second dielectric layers and a plurality of second conductive trace layers alternately stacked. The trace density of the first conductive trace layers is higher than the trace density of the second conductive trace layers. Otherwise, the first dielectric layer includes an inorganic material and the second dielectric layer includes an organic material. A manufacturing method of the silicon based substrate is also provided.

Abstract: A through-silicon via structure includes a substrate with a first side and a second side, a through-silicon hole connecting the first side and the second side and filled with a conductive material, a passivation layer disposed on and contacting the first side and covering the through-silicon hole, and a protection ring surrounding but not contacting the through-silicon hole and exposed by the first side and the second side. The protection ring is filled with an insulating material.

Abstract: A phase change memory is provided, which includes a semiconductor substrate having a first conductive type, buried word lines having a second conductive type, doped semiconductor layers having the first conductive type, memory cells, metal silicide layers, and bit lines. The buried word lines are disposed in the semiconductor substrate. Each buried word line includes a line-shaped main portion extended along a first direction and protrusion portions. Each protrusion portion is connected to one long side of the line-shaped main portion. Each doped semiconductor layer is disposed on one protrusion portion. Each memory cell includes a phase change material layer and is disposed on and electrically connected to one of the doped semiconductor layers. Each metal silicide layer is disposed on one of the line-shaped main portions. Each bit line is connected to memory cells disposed on the word lines in a second direction substantially perpendicular to the first direction.

Abstract: An electrical fuse structure is disclosed. The electrical fuse structure includes a fuse element disposed on surface of a semiconductor substrate, a cathode electrically connected to one end of the fuse element, and an anode electrically connected to another end of the fuse element. Specifically, a compressive stress layer is disposed on at least a portion of the fuse element.

Abstract: A phase change memory and the method for manufacturing the same are disclosed. The phase change memory includes a word line, a phase change element, a plurality of heating parts, and a plurality of bit lines. The phase change material layer is electrically connected to the word line and the heating parts. Each heating part is electrically connected to a respective bit line.

Abstract: A method for fabricating through-silicon via structure is disclosed. The method includes the steps of: providing a semiconductor substrate; forming at least one semiconductor device on surface of the semiconductor substrate; forming a dielectric layer on the semiconductor device, in which the dielectric layer includes at least one via hole; forming a first conductive layer on the dielectric layer and filling the via hole; performing an etching process to form a through-silicon via in the first conductive layer, the dielectric layer, and the semiconductor substrate; depositing a second conductive layer in the through-silicon via and partially on the first conductive layer; and planarizing a portion of the second conductive layer until reaching the surface of the first conductive layer.

Abstract: A through substrate via (TSV) process is provided. A substrate having a first side and a second side opposite the first side is provided. A plurality of holes is formed in the substrate at the first side. A first dielectric layer is formed on a sidewall and a bottom of the holes. A second dielectric layer is formed in the holes, wherein a material of the second dielectric layer is different from that of the first dielectric layer. A semiconductor device and an interconnect are formed on the substrate at the first side. At least a portion of the substrate at the second side is removed to expose the second dielectric layer in the holes. The second dielectric layer is removed. A conductive layer is formed in the holes.

Abstract: A through-silicon via structure includes a substrate with a first side and a second side, a through-silicon hole connecting the first side and the second side and filled with a conductive material, a passivation layer disposed on and contacting the first side and covering the through-silicon hole, and a protection ring surrounding but not contacting the through-silicon hole and exposed by the first side and the second side. The protection ring is filled with an insulating material.

Abstract: An electrical fuse structure is disclosed. The electrical fuse structure includes a fuse element disposed on surface of a semiconductor substrate, a cathode electrically connected to one end of the fuse element, and an anode electrically connected to another end of the fuse element. Specifically, a compressive stress layer is disposed on at least a portion of the fuse element.

Abstract: A semiconductor device with a TSV and a shelter is provided. The semiconductor device includes a substrate, a circuit area, at least a TSV and a shelter. The circuit area and the TSV are disposed on the substrate, and the TSV penetrates through the substrate. The shelter is disposed on the substrate and at least one part thereof is between the circuit area and the TSV in order to shelter EMI between the TSV and the circuit area. The novel structure prevents the circuits in the circuit area being affected by noise caused by TSV when TSV acts as a power pin.

Abstract: A phase change memory is provided, which includes a semiconductor substrate having a first conductive type, buried word lines having a second conductive type, doped semiconductor layers having the first conductive type, memory cells, metal silicide layers, and bit lines. The buried word lines are disposed in the semiconductor substrate. Each buried word line includes a line-shaped main portion extended along a first direction and protrusion portions. Each protrusion portion is connected to one long side of the line-shaped main portion. Each doped semiconductor layer is disposed on one protrusion portion. Each memory cell includes a phase change material layer and is disposed on and electrically connected to one of the doped semiconductor layers. Each metal silicide layer is disposed on one of the line-shaped main portions. Each bit line is connected to memory cells disposed on the word lines in a second direction substantially perpendicular to the first direction.

Abstract: An operating voltage tuning method for a static random access memory is disclosed. The static random access memory receives a periphery voltage and a memory cell voltage. The steps of the method mentioned above are shown as follows. First, perform a shmoo test on the static random access memory to obtain a shmoo test plot and a minimum operating voltage. Compare the minimum operating voltage with a preset specification. Position a specification position point on the line which the periphery voltage is equal to the memory cell voltage in the shmoo test plot corresponding to the preset specification. Fix one of the memory cell voltage and the periphery voltage and gradually decrease the other to test the static random access memory and obtain a failure bits distribution. Finally, tune process parameters of the static random access memory according to the specification position point and the failure bits distribution.

Abstract: An inverter structure is disclosed. The inverter structure includes an NMOS transistor and a PMOS transistor. Preferably, the NMOS transistor includes an n-type gate electrode and an n-type source/drain region, and the PMOS transistor includes a p-type gate electrode and a p-type source/drain region. Specifically, the n-type gate electrode and the p-type gate electrode are physically separated and electrically connected by a conductive contact.

Abstract: An operating voltage tuning method for a static random access memory is disclosed. The static random access memory receives a periphery voltage and a memory cell voltage. The steps of the method mentioned above are shown as follows. First, perform a shmoo test on the static random access memory to obtain a shmoo test plot and a minimum operating voltage. Compare the minimum operating voltage with a preset specification. Position a specification position point on the line which the periphery voltage is equal to the memory cell voltage in the shmoo test plot corresponding to the preset specification. Fix one of the memory cell voltage and the periphery voltage and gradually decrease the other to test the static random access memory and obtain a failure bits distribution. Finally, tune process parameters of the static random access memory according to the specification position point and the failure bits distribution.

Abstract: A through substrate via (TSV) process is provided. A substrate having a first side and a second side opposite the first side is provided. A plurality of holes is formed in the substrate at the first side. A first dielectric layer is formed on a sidewall and a bottom of the holes. A second dielectric layer is formed in the holes, wherein a material of the second dielectric layer is different from that of the first dielectric layer. A semiconductor device and an interconnect are formed on the substrate at the first side. At least a portion of the substrate at the second side is removed to expose the second dielectric layer in the holes. The second dielectric layer is removed. A conductive layer is formed in the holes.