Patents by Inventor Chien-Li Kuo

Chien-Li Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTERPOSER FABRICATING PROCESS AND WAFER PACKAGING STRUCTURE
    Publication number: 20150348892
    Abstract: An interposer fabricating process includes the following steps. A substrate, an oxide layer, and a dielectric layer are stacked from bottom to top, and an interconnect in the dielectric layer is provided, wherein the dielectric layer includes a stop layer contacting the oxide layer and the interconnect includes a metal structure having a barrier layer protruding from the stop layer. The substrate and the oxide layer are removed until exposing the stop layer and the barrier layer by a removing selectivity between the oxide layer and the stop layer. A wafer packaging structure formed by said interposer is also provided.
    Type: Application
    Filed: May 28, 2014
    Publication date: December 3, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Chien-Li Kuo
  • INTERPOSER AND METHOD OF FABRICATING THE SAME
    Publication number: 20150332996
    Abstract: The present invention provides an interposer including multiple circuit designs and an uppermost circuit design disposed on the circuit designs. A maximum exposure region is defined as a maximum size which can be defined by a single shot of a lithographic scanner. The sizes of the circuit designs below the uppermost circuit design are smaller than the size of the maximum exposure region. Therefore, the circuit designs are respectively formed by only a single shot of the lithographic scanner. The uppermost circuit design has a length greater than the length of the maximum exposure region, so that the circuit design is formed by stitching two photomasks lithographically.
    Type: Application
    Filed: May 19, 2014
    Publication date: November 19, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Li Kuo, Kuei-Sheng Wu, Ming-Tse Lin, Chung-Sung Chiang
  • Method Of Forming Chip With Through Silicon Via Electrode
    Publication number: 20150311117
    Abstract: The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening.
    Type: Application
    Filed: July 3, 2015
    Publication date: October 29, 2015
    Inventors: Ming-Tse Lin, Chu-Fu Lin, Chien-Li Kuo, Yung-Chang Lin
  • WAFER, PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20150311183
    Abstract: The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided. A wafer including a plurality of second dies is provided. A package step is carried out to package the array chip onto the wafer so as to electrically connect the first die and the second die. The present invention further provides a semiconductor wafer and a package structure.
    Type: Application
    Filed: May 26, 2014
    Publication date: October 29, 2015
    Inventor: Chien-Li Kuo
  • METHOD FOR FORMING SEMICONDUCTOR DEVICE
    Publication number: 20150303108
    Abstract: A semiconductor device includes a substrate with a front side and a back side, an ILD, disposed on the substrate, a cap layer disposed on the backside of the substrate, a TSV penetrating the cap layer, the substrate and the ILD, wherein a cap layer sidewall in the TSV juts out beyond the substrate sidewall the TSV with a predetermined distance, and a liner is disposed on the substrate sidewall, wherein the liner partially overlaps with the cap layer.
    Type: Application
    Filed: May 20, 2015
    Publication date: October 22, 2015
    Inventors: Chien-Li Kuo, Yung-Chang Lin
  • WAFER PACKAGE PROCESS
    Publication number: 20150279829
    Abstract: A wafer package process includes the following steps. A wafer with a plurality of first dies is provided. A plurality of second dies are bonded on the first dies by using flip chip technology, wherein the size of the first die is larger than that of the second die. A molding material is formed to entirely cover the second dies and the wafer. A through via is formed in the molding material. A conductive material is formed to fill the through via onto the molding material.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 1, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Chien-Li Kuo
  • Semiconductor device having through silicon trench shielding structure surrounding RF circuit
    Patent number: 9123730
    Abstract: The present invention provides a semiconductor device with a shielding structure. The semiconductor device includes a substrate, an RF circuit, a shielding structure and an interconnection system. The substrate includes an active side and a back side. The RF circuit is disposed on the active side of the substrate. The shielding structure is disposed on the active side and encompasses the RF circuit. The shielding structure is grounded. The shielding structure includes a shielding TST which does not penetrate through the substrate. The interconnection system is disposed on the active side of the substrate. The interconnection system includes a connection unit providing a signal to the RF circuit.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: September 1, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Li Kuo, Yung-Chang Lin, Ming-Tse Lin, Kuei-Sheng Wu, Chia-Fang Lin
  • Chip with through silicon via electrode and method of forming the same
    Patent number: 9123789
    Abstract: The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: September 1, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Tse Lin, Chu-Fu Lin, Chien-Li Kuo, Yung-Chang Lin
  • Interposer structure and manufacturing method thereof
    Patent number: 9117804
    Abstract: An interposer structure including a semiconductor substrate, a plurality of shallow trenches, a plurality of deep trenches and a plurality of metal damascene structures is provided. The semiconductor substrate has a first surface and a second surface opposite to each other. The shallow trenches are formed on the first surface in both of a first area and a second area of the semiconductor substrate and correspondingly a plurality of respective openings are formed on the first surface. The deep trenches extend from at least one of the shallow trenches toward the second surface in the second area and correspondingly a plurality of respective openings are formed on the second surface. The metal damascene structures are filled in both of the shallow trenches and the deep trenches. A manufacturing method for the aforementioned interposer structure is also provided.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: August 25, 2015
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventor: Chien-Li Kuo
  • INTEGRATED STRUCTURE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20150179516
    Abstract: A method for fabricating integrated structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon hole in the substrate; forming a patterned resist on the substrate, wherein the patterned resist comprises at least one opening corresponding to a redistribution layer (RDL) pattern and exposing the through-silicon hole and at least another opening corresponding to another redistribution layer (RDL) pattern and connecting to the at least one opening; and forming a conductive layer to fill the through-silicon hole, the at least one opening and the at least another opening in the patterned resist so as to form a through-silicon via, a through-silicon via RDL pattern and another RDL pattern in one structure.
    Type: Application
    Filed: December 25, 2013
    Publication date: June 25, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hung Chen, Ming-Tse Lin, Yung-Chang Lin, Chien-Li Kuo
  • HYBRID INTERCONNECT STRUCTURE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20150179580
    Abstract: A method for fabricating hybrid interconnect structure is disclosed. The method includes the steps of: providing a material layer; forming a through-silicon hole in the material layer; forming a patterned resist on the material layer, wherein the patterned resist comprises at least an opening for exposing the through-silicon hole; and forming a conductive layer to fill the through-silicon hole and the opening in the patterned resist.
    Type: Application
    Filed: December 24, 2013
    Publication date: June 25, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Li Kuo, Chun-Hung Chen, Yung-Chang Lin, Ming-Tse Lin
  • Package structure having silicon through vias connected to ground potential
    Patent number: 9048223
    Abstract: A package structure having silicon through vias connected to ground potential is disclosed, comprising a first device, a second device and a conductive adhesive disposed between the first device and the second device. The first device comprises a substrate having a front surface and a back surface, and a plurality of through silicon vias filled with a conductor formed within the substrate. The first device is externally connected to the second device by wire bonding.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: June 2, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Li Kuo, Yung-Chang Lin, Ming-Tse Lin
  • Semiconductor structure
    Patent number: 9024416
    Abstract: A semiconductor structure is provided. The semiconductor structure includes an interposer structure. The interposer structure includes an interposer substrate, a ground, through vias, a dielectric layer, and an inductor. The through vias are formed in the interposer substrate and electrically connected to the ground. The dielectric layer is on the interposer substrate. The inductor is on the dielectric layer.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: May 5, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Hung Chen, Ming-Tse Lin, Chien-Li Kuo, Kuei-Sheng Wu
  • Through silicon via process
    Patent number: 9012324
    Abstract: A through silicon via process includes the following steps. A substrate having a front side and a back side is provided. A passivation layer is formed on the back side of the substrate. An oxide layer is formed on the passivation layer.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: April 21, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Ching-Wei Hsu, Szu-Hao Lai, Huei-Ru Tsai, Tsai-Yu Wen, Ching-Li Yang, Chien-Li Kuo
  • INTERPOSER STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20150076694
    Abstract: An interposer structure including a semiconductor substrate, a plurality of shallow trenches, a plurality of deep trenches and a plurality of metal damascene structures is provided. The semiconductor substrate has a first surface and a second surface opposite to each other. The shallow trenches are formed on the first surface in both of a first area and a second area of the semiconductor substrate and correspondingly a plurality of respective openings are formed on the first surface. The deep trenches extend from at least one of the shallow trenches toward the second surface in the second area and correspondingly a plurality of respective openings are formed on the second surface. The metal damascene structures are filled in both of the shallow trenches and the deep trenches. A manufacturing method for the aforementioned interposer structure is also provided.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 19, 2015
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventor: Chien-Li KUO
  • PACKAGE STRUCTURE HAVING SILICON THROUGH VIAS CONNECTED TO GROUND POTENTIAL
    Publication number: 20150061151
    Abstract: A package structure having silicon through vias connected to ground potential is disclosed, comprising a first device, a second device and a conductive adhesive disposed between the first device and the second device. The first device comprises a substrate having a front surface and a back surface, and a plurality of through silicon vias filled with a conductor formed within the substrate. The first device is externally connected to the second device by wire bonding.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 5, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Li Kuo, Yung-Chang Lin, Ming-Tse Lin
  • SEMICONDUCTOR STRUCTURE
    Publication number: 20150041952
    Abstract: A semiconductor structure is provided. The semiconductor structure includes an interposer structure. The interposer structure includes an interposer substrate, a ground, through vias, a dielectric layer, and an inductor. The through vias are formed in the interposer substrate and electrically connected to the ground. The dielectric layer is on the interposer substrate. The inductor is on the dielectric layer.
    Type: Application
    Filed: August 12, 2013
    Publication date: February 12, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hung Chen, Ming-Tse Lin, Chien-Li Kuo, Kuei-Sheng Wu
  • Semiconductor Device Having Shielding Structure
    Publication number: 20150014828
    Abstract: The present invention provides a semiconductor device with a shielding structure. The semiconductor device includes a substrate, an RF circuit, a shielding structure and an interconnection system. The substrate includes an active side and a back side. The RF circuit is disposed on the active side of the substrate. The shielding structure is disposed on the active side and encompasses the RF circuit. The shielding structure is grounded. The shielding structure includes a shielding TST which does not penetrate through the substrate. The interconnection system is disposed on the active side of the substrate. The interconnection system includes a connecting unit electrically connect a signal to the RF circuit.
    Type: Application
    Filed: July 11, 2013
    Publication date: January 15, 2015
    Inventors: Chien-Li Kuo, Yung-Chang Lin, Ming-Tse Lin, Kuei-Sheng Wu, Chia-Fang Lin
  • Method for forming semiconductor structure having through silicon via for signal and shielding structure
    Patent number: 8916471
    Abstract: A method for forming a through silicon via for signal and a shielding structure is provided. A substrate is provided and a region is defined on the substrate. A radio frequency (RF) circuit is formed in the region on the substrate. A through silicon trench (TST) and a through silicon via (TSV) are formed simultaneously, wherein the TST encompasses the region to serve as a shielding structure for the RF circuit. A metal interconnection system is formed on the substrate, wherein the metal interconnection system comprises a connection unit that electrically connects the TSV to the RF circuit to provide a voltage signal.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: December 23, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Li Yang, Chien-Li Kuo, Chung-Sung Chiang, Yu-Han Tsai, Chun-Wei Kang
  • THROUGH SILICON VIA AND PROCESS THEREOF
    Publication number: 20140346645
    Abstract: A through silicon via includes a substrate and a conductive plug. The substrate has a hole in a side. The conductive plug is disposed in the hole, and the conductive plug having an upper part protruding from the side, wherein the upper part has a top part and a bottom part, and the top part is finer than the bottom part. Moreover, a through silicon via process formed said through silicon via is also provided, which includes the following step. A hole is formed in a substrate from a side. A first conductive material is formed to cover the hole and the side. A patterned photoresist is formed to cover the side but exposing the hole. A second conductive material is formed on the exposed first conductive material. The patterned photoresist is removed. The first conductive material on the side is removed to form a conductive plug in the hole.
    Type: Application
    Filed: May 23, 2013
    Publication date: November 27, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Li Kuo, Chun-Hung Chen, Ming-Tse Lin, Yung-Chang Lin