Patents by Inventor Chien-Li Kuo

Chien-Li Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • THROUGH SILICON VIA AND PROCESS THEREOF
    Publication number: 20140346645
    Abstract: A through silicon via includes a substrate and a conductive plug. The substrate has a hole in a side. The conductive plug is disposed in the hole, and the conductive plug having an upper part protruding from the side, wherein the upper part has a top part and a bottom part, and the top part is finer than the bottom part. Moreover, a through silicon via process formed said through silicon via is also provided, which includes the following step. A hole is formed in a substrate from a side. A first conductive material is formed to cover the hole and the side. A patterned photoresist is formed to cover the side but exposing the hole. A second conductive material is formed on the exposed first conductive material. The patterned photoresist is removed. The first conductive material on the side is removed to form a conductive plug in the hole.
    Type: Application
    Filed: May 23, 2013
    Publication date: November 27, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Li Kuo, Chun-Hung Chen, Ming-Tse Lin, Yung-Chang Lin
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR TESTING THE SAME
    Publication number: 20140332952
    Abstract: A semiconductor structure comprising a substrate, a dielectric layer, a conductor post, a first conductive layer structure and a second conductive layer structure is provided. The substrate comprises an opening structure. The dielectric layer is disposed on a sidewall of the opening structure. The conductor structure is disposed in the opening structure and covers the dielectric layer. The first and second conductive layer structures are electrically connected to the conductor post. A voltage difference is existed between the first and second conductive layer structures, such that a current is passing through the first conductive layer structure, the opening structure and second conductive layer structure. A resistance values is related to the voltage difference and the current. A dimension of the opening structure is 10 times greater than a dimension of the first and second conductive layer structures.
    Type: Application
    Filed: May 9, 2013
    Publication date: November 13, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Li Kuo, Yung-Chang Lin, Chun-Ting Yeh, Kuei-Sheng Wu
  • Anti-fuse structure and programming method thereof
    Patent number: 8884398
    Abstract: A method of programming an anti-fuse includes steps as follows. First, an insulating layer is provided. An anti-fuse region is defined on the insulating layer. An anti-fuse is embedded within the anti-fuse region of the insulating layer. The anti-fuse includes at least a first conductor and a second conductor. Then, part of the insulating layer is removed by a laser to form an anti-fuse opening in the insulating layer. Part of the first conductor and part of the second conductor are exposed through the anti-fuse opening. After that, a under bump metallurgy layer is formed in the anti-fuse opening to connect the first conductor and the second conductor electrically.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chu-Fu Lin, Chien-Li Kuo, Ching-Li Yang
  • ANTI-FUSE STRUCTURE AND PROGRAMMING METHOD THEREOF
    Publication number: 20140291801
    Abstract: A method of programming an anti-fuse includes steps as follows. First, an insulating layer is provided. An anti-fuse region is defined on the insulating layer. An anti-fuse is embedded within the anti-fuse region of the insulating layer. The anti-fuse includes at least a first conductor and a second conductor. Then, part of the insulating layer is removed by a laser to form an anti-fuse opening in the insulating layer. Part of the first conductor and part of the second conductor are exposed through the anti-fuse opening. After that, a under bump metallurgy layer is formed in the anti-fuse opening to connect the first conductor and the second conductor electrically.
    Type: Application
    Filed: April 1, 2013
    Publication date: October 2, 2014
    Inventors: Chu-Fu Lin, Chien-Li Kuo, Ching-Li Yang
  • Chip With Through Silicon Via Electrode And Method Of Forming The Same
    Publication number: 20140203394
    Abstract: The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening.
    Type: Application
    Filed: January 23, 2013
    Publication date: July 24, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Tse Lin, Chu-Fu Lin, Chien-Li Kuo, Yung-Chang Lin
  • Through silicon via structure having protection ring
    Patent number: 8692359
    Abstract: A method of fabricating a semiconductor device includes the following steps. A semiconductor substrate having a first side and a second side facing to the first side is provided. At least an opening is disposed in the semiconductor substrate of a protection region defined in the first side. A first material layer is formed on the first side and the second side, and the first material layer partially fills the opening. Subsequently, a part of the first material layer on the first side and outside the protection region is removed. A second material layer is formed on the first side and the second side, and the second material layer fills the opening. Then, a part of the second material layer on the first side and outside the protection region is removed. Finally, the remaining first material layer and the remaining second material layer on the first side are planarized.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: April 8, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Yung-Chang Lin, Chien-Li Kuo, Ming-Tse Lin, Sun-Chieh Chien
  • CAPACITOR STRUCTURE AND FABRICATING METHOD THEREOF
    Publication number: 20140061855
    Abstract: A capacitor structure includes a first conductive structure, a dielectric structure, a first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode. The first conductive structure is disposed over a substrate. The dielectric structure is disposed over the substrate and partially enclosing the first conductive structure. The dielectric structure has a trench. A first surface of the first conductive structure is exposed through the trench of the dielectric structure. The first capacitor electrode is disposed on a bottom and a sidewall of the trench. The first capacitor electrode is electrically contacted with the first surface of the first conductive structure. The capacitor dielectric layer is disposed on a surface of the first capacitor electrode. The second capacitor electrode is disposed on a surface of the capacitor dielectric layer and filled in the trench.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chien-Li KUO, Kuei-Sheng WU, Ju-Bao ZHANG, Rui-Huang CHENG, Xing-Hua ZHANG, Hong LIAO
  • THROUGH SILICON VIA PROCESS
    Publication number: 20140057434
    Abstract: A through silicon via process includes the following steps. A substrate having a front side and a back side is provided. A passivation layer is formed on the back side of the substrate. An oxide layer is formed on the passivation layer.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Inventors: Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Ching-Wei Hsu, Szu-Hao Lai, Huei-Ru Tsai, Tsai-Yu Wen, Ching-Li Yang, Chien-Li Kuo
  • SEMICONDUCTOR DEVICE
    Publication number: 20130334669
    Abstract: A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Inventors: Chien-Li Kuo, Yung-Chang Lin
  • SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
    Publication number: 20130334699
    Abstract: A semiconductor device includes a substrate with a front side and a back side, an ILD, disposed on the substrate, a cap layer disposed on the backside of the substrate, a TSV penetrating the cap layer, the substrate and the ILD, wherein a cap layer sidewall in the TSV juts out beyond the substrate sidewall the TSV with a predetermined distance, and a liner is disposed on the substrate sidewall, wherein the liner partially overlaps with the cap layer.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Inventors: Chien-Li Kuo, Yung-Chang Lin
  • Inverter structure and method for fabricating the same
    Patent number: 8546890
    Abstract: An inverter structure is disclosed. The inverter structure includes an NMOS transistor and a PMOS transistor. Preferably, the NMOS transistor includes an n-type gate electrode and an n-type source/drain region, and the PMOS transistor includes a p-type gate electrode and a p-type source/drain region. Specifically, the n-type gate electrode and the p-type gate electrode are physically separated and electrically connected by a conductive contact.
    Type: Grant
    Filed: November 27, 2008
    Date of Patent: October 1, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Li Kuo, Chia-Chun Sun, Chuan-Hsien Fu, Chun-Liang Hou, Yun-San Huang
  • Capacitor structure and method of forming the same
    Patent number: 8525296
    Abstract: The present invention provides a capacitor structure, comprising a substrate, a TSV, a dielectric layer and a doped region. The substrate includes a first surface and a second surface, which are disposed oppositely to each other. The TSV penetrates through the first surface and the second surface. The dielectric layer is disposed in the substrate and encompasses the TSV. The doped region is disposed between the dielectric layer and the substrate. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: September 3, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Yung-Chang Lin, Chien-Li Kuo
  • TSV structure and method for forming the same
    Patent number: 8519515
    Abstract: A TSV structure includes a through via connecting a first side and a second side of a wafer, a conductive layer which fills up the through via, a through via dielectric ring surrounding and directly contacting the conductive layer, a first conductive ring surrounding and directly contacting the through via dielectric ring as well as a first dielectric ring surrounding and directly contacting the first conductive ring and surrounded by the wafer.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: August 27, 2013
    Assignee: United Microlectronics Corp.
    Inventors: Chien-Li Kuo, Chia-Fang Lin
  • Method for predicting tolerable spacing between conductors in semiconductor process
    Patent number: 8516400
    Abstract: A method for predicting tolerable contact-to-gate spacing is provided. At first, a wafer with a plurality of source/drain contacts are provided. Then, a plurality of testing gate lines are formed on the wafer by using a photomask. In one die, there are different contact-to-gate distances ranging from d+?d to d??d wherein d is the standard spacing and ?d<d. Then, the wafer is inspected to find failure counts corresponding to each contact-to-gate distance. The tolerable spacing is determined according to the failure counts and the contact-to-gate distances based on a statistical method.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: August 20, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Li Kuo, Wen-Jung Liao, Jiun-Hau Liao, Min-Chin Hsieh, Chun-Liang Hou, Shuen-Cheng Lei
  • SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    Publication number: 20130140708
    Abstract: A method of fabricating a semiconductor device includes the following steps. A semiconductor substrate having a first side and a second side facing to the first side is provided. At least an opening is disposed in the semiconductor substrate of a protection region defined in the first side. A first material layer is formed on the first side and the second side, and the first material layer partially fills the opening. Subsequently, a part of the first material layer on the first side and outside the protection region is removed. A second material layer is formed on the first side and the second side, and the second material layer fills the opening. Then, a part of the second material layer on the first side and outside the protection region is removed. Finally, the remaining first material layer and the remaining second material layer on the first side are planarized.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Inventors: Yung-Chang Lin, Chien-Li Kuo, Ming-Tse Lin, Sun-Chieh Chien
  • Chip stacking structure
    Patent number: 8441134
    Abstract: A chip stacking structure includes a first chip and a second chip. The first chip includes a surface having a first group of pads formed thereon, and the second chip includes a surface having a second group of pads formed thereon. The second group of pads is bonded onto the first group of pads to define a plurality of capillary passages extending in a same direction. The chip stacking structure further includes an underfill filling up interspaces between the first chip and the second chip. The chip stacking structure is capable of avoiding chip deformation and cracking during a bonding process.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: May 14, 2013
    Assignee: United Microelectronics Corporation
    Inventors: Chien-Li Kuo, Yung-Chang Lin, Ming-Tse Lin
  • CHIP STACKING STRUCTURE
    Publication number: 20130062780
    Abstract: A chip stacking structure includes a first chip and a second chip. The first chip includes a surface having a first group of pads formed thereon, and the second chip includes a surface having a second group of pads formed thereon. The second group of pads is bonded onto the first group of pads to define a plurality of capillary passages extending in a same direction. The chip stacking structure further includes an underfill filling up interspaces between the first chip and the second chip. The chip stacking structure is capable of avoiding chip deformation and cracking during a bonding process.
    Type: Application
    Filed: September 9, 2011
    Publication date: March 14, 2013
    Applicant: United Microelectronics Corporation
    Inventors: Chien-Li KUO, Yung-Chang Lin, Ming-Tse Lin
  • Probe Calibration Device and Calibration Method
    Publication number: 20130038336
    Abstract: A calibration device applied for a test apparatus with at least a first probe and a second probe, the calibration device comprising: a first testing region and a second testing region, the first testing region and the second testing region divides into n×n sensing units respectively, the first testing region for generating n×n average electricity corresponding to a contact degree of the first probe contacted with the calibration device, and the second testing region for generating another n×n average electricity corresponding to a contact degree of the second probe contacted with the calibration device, and the pitch is the distance between the center of the first testing region to the center of the second testing region that is the same as that of the center of the first probe to the center of the second probe.
    Type: Application
    Filed: August 12, 2011
    Publication date: February 14, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Jie-Wei SUN, Chao-Hsien Wu, Chia-Chun Sun, Yun-San Huang, Chien-Li Kuo
  • TSV STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20130015504
    Abstract: A TSV structure includes a wafer including a first side and a second side, a through via connecting the first side and the second side, a through via dielectric layer covering the inner wall of the through via, a conductive layer which fills up the through via and consists of a single material to be a seamless TSV structure, a first dielectric layer covering the first side and surrounding the conductive layer as well as a second dielectric layer covering the second side and part of the through via dielectric layer but partially covered by the conductive layer.
    Type: Application
    Filed: July 11, 2011
    Publication date: January 17, 2013
    Inventors: Chien-Li Kuo, Chin-Sheng Yang, Ming-Tse Lin
  • SEMICONDUCTOR DEVICE
    Publication number: 20120261834
    Abstract: A semiconductor device with a TSV and a shelter is provided. The semiconductor device includes a substrate, a circuit area, at least a TSV and a shelter. The circuit area and the TSV are disposed on the substrate, and the TSV penetrates through the substrate. The shelter is disposed on the substrate and at least one part thereof is between the circuit area and the TSV in order to shelter EMI between the TSV and the circuit area. The novel structure prevents the circuits in the circuit area being affected by noise caused by TSV when TSV acts as a power pin.
    Type: Application
    Filed: June 22, 2012
    Publication date: October 18, 2012
    Inventor: Chien-Li Kuo