Abstract: A color electrophoretic display and a display method thereof are provided. The color electrophoretic display comprises an achromatic color particle and a plurality of chromatic color particles. The display method of the color electrophoretic display comprises turning on a stylus mode, providing an assigned stylus color, sensing a movement of the stylus to output a black trace, and transferring the black trace into a color trace of the assigned stylus color when the stylus movement stops. The black trace is shown when the achromatic color particle and the chromatic color particles move toward a top electrode, and a refresh time of the color of the black trace is smaller than 50 ms. The color of the assigned stylus color and the color of the black trace have brightness difference and at least one of the hue differences and the saturation differences.

Abstract: The disclosure describes embodiments of an apparatus including a first gas chromatograph including a fluid inlet, a fluid outlet, and a first temperature control. A controller is coupled to the first temperature control and includes logic to apply a first temperature profile to the first temperature control to heat, cool, or both heat and cool the first gas chromatograph. Other embodiments are disclosed and claimed.

Abstract: Methods and apparatuses for an operation for a channel state information upsampling in a wireless communication system. A method of BS includes: receiving, from a UE, feedback information including at least one SB level precoder; identifying, based on the at least one SB level precoder, a mapping function to perform an up-sampling operation; performing, based on the mapping function, the up-sampling operation to the at least one SB level precoder; and identifying, based on the up-sampling operation, at least one RB level precoder from the at least one SB level precoder for a precoder gain of the BS.

Abstract: A method of controlling a wafer stage includes moving the wafer stage to position an immersion hood over a first sensor in the wafer stage. The method further includes moving the wafer stage to position the immersion hood over a second sensor in the wafer stage. The method further includes moving the wafer stage to position the immersion hood over a first particle capture area on the wafer stage after moving the wafer stage to position the immersion hood over the second sensor. The method further includes moving the wafer stage to define a routing track over the first particle capture area. The method further includes moving the wafer stage to position the immersion hood over an area for receiving a wafer on the wafer stage after defining the routing track over the first particle capture area.

Abstract: In an embodiment, a method includes forming a plurality of semiconductor fins over a substrate, the plurality of semiconductor fins comprising a first fin, a second fin, a third fin, and a fourth fin; forming a first dielectric layer over the plurality of semiconductor fins, the first dielectric layer filling an entirety of a first trench between the first fin and the second fin; forming a second dielectric layer over the first dielectric layer, the second dielectric layer filling an entirety of a second trench between the second fin and the third fin, the forming the second dielectric layer comprising: forming an oxynitride layer; and forming an oxide layer; and forming a third dielectric layer over the second dielectric layer, the third dielectric layer filling an entirety of a third trench between the third fin and the fourth fin.

Abstract: Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.

Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

Abstract: An induction motor with on-rotor slip power recovery may have a rotor and a stator element. The rotor element has a rotor winding system with a number of winding units wound-distributed for inducing a rotor magnetic field. Each winding unit has an induction and an augmentation subwinding. The induction subwinding has two legs of each a number of induction conductor segments. The induction subwinding induces an emf that drives a rotor current in the rotor winding system to generate a basic induction component for the rotor magnetic field when the induction conductor segments move in the stator element. The augmentation subwinding has two legs of each a number of augmentation conductor segments aligned parallel to the induction conductor segments. The augmentation subwinding being wound that the two legs of augmentation conductor segments are immediately next to each other and positioned mid-way between the two legs of induction conductor segments.

Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.

Abstract: Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.

Abstract: A power adjusting system and method are provided. The power adjusting method is applicable to the power adjusting system. The power adjusting method includes processes of: detecting an input voltage of the power adjusting system by a detector circuit of the power adjusting system; detecting voltages of first terminals of high-side switches of the power adjusting system by the detector circuit; detecting a voltage of a battery by the detector circuit; detecting currents flowing to the high-side switches by the detector circuit; detecting a current flowing through the battery; detecting a current flowing through a motor; determining whether or not abnormal conditions occur in the power adjusting system and the motor according to the detected voltages and currents, and accordingly controlling operations of the high-side switches and low-side switches and a switching circuit of the power adjusting system, by a controller circuit of the power adjusting system.

Abstract: A knob device for disposing on a touch screen, comprising a base provided with a plurality of recovery elastic components; and an operating cap disposed on the base. The operating cap have a rotation stroke and a pressing stroke, and is provided with a plurality of touch control pads, each of the pads has a working surface. The working surface of at least one of the touch control pads is not at a same height as the working surfaces of the other touch control pads. When the rotation stroke is performed, the working surfaces of some of the touch control pads contact the touch screen to activate a rotational touch control. When the pressing stroke is performed, the working surfaces of the touch control pads contact the touch screen jointly to activate a click and touch control.

Abstract: The disclosure provides a fabric structure, which includes a base fabric and a coating layer. The base fabric is woven from multiple yarns. Each of the yarns is composed of a fiber. The coating layer is disposed on the base fabric. The fiber and the coating layer do not include polyvinyl chloride. A manufacturing method of the fabric structure is also provided.

Abstract: In an embodiment, a method includes forming a plurality of semiconductor fins over a substrate, the plurality of semiconductor fins comprising a first fin, a second fin, a third fin, and a fourth fin; forming a first dielectric layer over the plurality of semiconductor fins, the first dielectric layer filling an entirety of a first trench between the first fin and the second fin; forming a second dielectric layer over the first dielectric layer, the second dielectric layer filling an entirety of a second trench between the second fin and the third fin, the forming the second dielectric layer comprising: forming an oxynitride layer; and forming an oxide layer; and forming a third dielectric layer over the second dielectric layer, the third dielectric layer filling an entirety of a third trench between the third fin and the fourth fin.

Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.

Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. At least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.

Abstract: An inspection apparatus includes: an inspection apparatus includes: a stage configured to receive a photomask; a radiation source configured to emit a first radiation beam for inspecting the photomask; and an aperture stop configured to receive a second radiation beam reflected from the photomask through an aperture of the aperture stop, wherein the aperture is tangent at a center of the aperture stop.

Abstract: An opening is formed through a dielectric material layer to physically expose a top surface of a conductive material portion in, or over, a substrate. A metallic nitride liner is formed on a sidewall of the opening and on the top surface of the conductive material portion. A metallic adhesion layer including an alloy of copper and at least one transition metal that is not copper is formed on an inner sidewall of the metallic nitride liner. A copper fill material portion may be formed on an inner sidewall of the metallic adhesion layer. The metallic adhesion layer is thermally stable, and remains free of holes during subsequent thermal processes, which may include reflow of the copper fill material portion. An additional copper fill material portion may be optionally deposited after a reflow process.