Patents by Inventor Chien Lin

Chien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220201173
    Abstract: A portable electronic device and a customized image-capturing module thereof are provided. The customized image-capturing module includes a carrier substrate, an image-capturing chip, and a lens assembly. The carrier substrate includes a carrier body, a plurality of first conductive pads, and a plurality of second conductive pads. The image-capturing chip is disposed inside a concave space of the carrier body, and the image-capturing chip includes a plurality of conductive chip pads. The second conductive pads are exposed from a bottom side of the carrier body, the conductive chip pads are electrically connected to the second conductive pads through the first conductive pads, respectively, so that when the customized image-capturing module is partially disposed inside a receiving space and positioned between two electronic elements, the second conductive pads can be electrically connected to conductive substrate pads of a circuit substrate through soldering materials, respectively.
    Type: Application
    Filed: July 23, 2021
    Publication date: June 23, 2022
    Inventors: TSENG-CHIEH LEE, KUNG-AN LIN, Chih-Yuan Chuang, CHIEN-CHE TING
  • Publication number: 20220199513
    Abstract: A wiring board includes an insulating layer, a wiring layer and a plurality of conductive columns. The insulating layer has a first surface and a second surface opposite to the first surface. The wiring layer is disposed in the insulating layer and has a third surface and a fourth surface opposite to the third surface. The insulating layer covers the third surface, and the second surface of the insulating layer is flush with the fourth surface of the wiring layer. The conductive columns are disposed in the insulating layer and connected to the wiring layer. The conductive columns extend from the third surface of the wiring layer to the first surface of the insulating layer, and protrude from the first surface.
    Type: Application
    Filed: March 11, 2022
    Publication date: June 23, 2022
    Inventors: Chun-Hao CHEN, Chia-Lung LIN, Chien-Hsiang CHOU, Yi-Lin CHIANG, Chien-Chen LIN
  • Publication number: 20220199306
    Abstract: A transformer includes a bobbin. The bobbin includes a main body, a connection member, and a terminal base. The main body is wound by a coil. Two sides of the connection member are respectively connected to the main body and the terminal base. A plurality of connection terminals of the coil extend to the terminal base through a wire trough of the main body and are connected to pins of the terminal base. The connection member is cut off by automated machining, and the terminal base is mounted on a surface of a housing of the transformer, and no pin is disposed on the housing. Hence, the overall size of the transformer is effectively reduced.
    Type: Application
    Filed: March 29, 2021
    Publication date: June 23, 2022
    Inventors: Po-Chien Chou, Che-Shih Lin, Yi-Wei Su
  • Patent number: 11367784
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. At least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: June 21, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chien Lin, Cheng-Han Lee, Shih-Chieh Chang, Shu Kuan
  • Patent number: 11368146
    Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: June 21, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Yuan Wu, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Yuan-Hui Chen, Cheng-Yang Tsai, Ruei-Yau Chen, Cheng-Tsung Ku, Zhi-Hong Huang, Yu-Lin Chen
  • Patent number: 11366358
    Abstract: A display apparatus includes a display panel and a switching panel disposed outside the display panel. The switching panel includes a first base, first and second electrodes disposed on the first base, a second base, third and fourth electrodes disposed on the second base, and a liquid crystal layer disposed between the first base and the second base. When the display apparatus is operated in a first anti-peep mode, the first electrode and the second electrode disposed on the first base have a first AC driving signal and a second AC driving signal respectively, and the third electrode and the fourth electrode disposed on the second base have DC reference signals respectively, wherein the first AC driving signal and the second AC driving signal are in synchronization.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: June 21, 2022
    Assignee: Au Optronics Corporation
    Inventors: Cian-Rou Wu, Kun-Cheng Tien, Chien-Huang Liao, Chin-An Lin
  • Patent number: 11358365
    Abstract: A splicable environmentally-friendly non-PVC advertising cloth made of a woven structure, wherein the advertising cloth comprising a mesh base layer (40); a first adhesion-promoting structural layer (10), which is a refractory and waterproof layer covering the front surface (43) and the rear surface (44) of the mesh base layer (40); a second adhesion-promoting structural layer (20) coated on the first surface (13) of the first adhesion-promoting structure layer (10); and a third adhesion-promoting structural layer (30) coated on the upper surface (24) of the second adhesion-promoting structure layer (20), therefore, waterproof and ink-absorbing structure arranged on a mesh base (40) layer, and the width of the advertising cloth (50) can be spliced unlimitedly as required by using high frequency splicing, making the environmentally friendly advertising cloth more applicable also improving the overall advertising effect and quality.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: June 14, 2022
    Assignee: Taya Canvas (Shanghai) Company Limited
    Inventor: I-Chien Lin
  • Patent number: 11360206
    Abstract: The present invention provides a detection device and a method with simplified computing manner A transmitter transmits detection signals to an environment to detect a target. At least a portion of the detection signals are reflected by the target to generate a plurality of reflection signals. A receiver comprises a plurality of receiving units. Each of the receiving units receives the reflection signals to generate a receiving signal. A processing module connected to the receiver includes a conversion unit, an integration unit and a computing unit. The conversion unit converts the receiving signals into transformation signals by a time-domain to frequency-domain transformation. The integration unit integrates the transformation signals into a first integration signal and a second integration signal. The computing unit decomposes the first integration signal and the second integration signal to 1D arrays.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: June 14, 2022
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Ta-Sung Lee, Kuan-Hen Lin, Yu-Chien Lin, Yun-Han Pan
  • Patent number: 11361998
    Abstract: A method for manufacturing an electronic device is provided. The method includes the following steps: providing a first mother substrate including a plurality of first substrate areas; performing a first half-cutting step on the first mother substrate to produce a first crack to define the plurality of first substrate areas; disposing a first optical film on the first mother substrate having the first crack, wherein the first optical film has a first cutting region corresponding to the first crack; performing a first cutting step in the first cutting region of the first optical film; and separating the plurality of first substrate areas to form a plurality of first substrates.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: June 14, 2022
    Assignee: INNOLUX CORPORATION
    Inventors: I-Chang Liang, Chien-Lin Lin, Chin-Lung Ting
  • Patent number: 11353501
    Abstract: A wafer inspection method, wherein a motorized chuck stage is controlled by a control rod to be displaced between an upper position and a lower position along Z-axis direction, to change a relative position of a wafer on the motorized chuck stage relative to a probe. The control rod is movable between an upper and an lower limit positions. The wafer inspection method includes: determining a position of the control rod based on a measurement signal; determining a first moving direction and a moving distance of the control rod based on a change of the measurement signal; generating a control signal based on the moving distance of the control rod; controlling the motorized chuck stage to be displaced along a second moving direction opposite to the first moving direction; and controlling an objective lens module to keep focusing on the wafer when the motorized chuck stage is on the move.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: June 7, 2022
    Assignee: MPI CORPORATION
    Inventors: Lin-Lin Chih, Chien-Hung Chen, Guan-Jhih Liou, Yu-Hsun Hsu
  • Publication number: 20220171688
    Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.
    Type: Application
    Filed: February 18, 2022
    Publication date: June 2, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hung CHANG, Atul KATOCH, Chia-En HUANG, Ching-Wei WU, Donald G. MIKAN, JR., Hao-I YANG, Kao-Cheng LIN, Ming-Chien TSAI, Saman M.I. ADHAM, Tsung-Yung CHANG, Uppu Sharath CHANDRA
  • Patent number: 11348847
    Abstract: The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit. Each of the oscillators has an enable terminal, a voltage terminal and an output terminal, wherein the enable terminals are connected to a common enable terminal. The driving circuit receives the output terminals of the oscillators and increases a driving level of a selected one of the output terminals as a frequency output.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: May 31, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Yuan Wu, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Yuan-Hui Chen, Ruei-Yau Chen, Cheng-Tsung Ku, Zhi-Hong Huang, Cheng-Yang Tsai, Yu-Lin Chen
  • Publication number: 20220165866
    Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed directly on the gate.
    Type: Application
    Filed: January 6, 2021
    Publication date: May 26, 2022
    Inventors: Chih-Wei Chang, Yao-Hsien Chung, Shih-Wei Su, Hao-Hsuan Chang, Da-Jun Lin, Ting-An Chien, Bin-Siang Tsai
  • Publication number: 20220165776
    Abstract: A pixel array may include air gap reflection structures under a photodiode of a pixel sensor to reflect photons that would otherwise partially refract or scatter through a bottom surface of a photodiode. The air gap reflection structures may reflect photons upward toward the photodiode so that the photons may be absorbed by the photodiode. This may increase the quantity of photons absorbed by the photodiode, which may increase the quantum efficiency of the pixel sensor and the pixel array.
    Type: Application
    Filed: November 20, 2020
    Publication date: May 26, 2022
    Inventors: Jyun-Hao LIN, Feng-Chien HSIEH, Yun-Wei CHENG, Kuo-Cheng LEE
  • Patent number: 11340398
    Abstract: A waveguide structure includes a first surface having a first width, a second surface having a second width, the second surface being opposite to the first surface, and a sidewall surface connecting the first surface and the second surface. The first width is greater than the second width.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: May 24, 2022
    Assignee: ARTILUX, INC.
    Inventors: Szu-Lin Cheng, Chien-Yu Chen, Han-Din Liu, Chia-Peng Lin, Chung-Chih Lin, Yun-Chung Na, Pin-Tso Lin, Tsung-Ting Wu, Yu-Hsuan Liu, Kuan-Chen Chu
  • Patent number: 11342340
    Abstract: A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yangsyu Lin, Chi-Lung Lee, Chien-Chi Tien, Chiting Cheng
  • Publication number: 20220158026
    Abstract: A light-emitting diode is provided. The light-emitting diode includes a P-type semiconductor layer, a N-type semiconductor layer, and a light-emitting stack located therebetween. The light-emitting stack includes a plurality of well layers and a plurality of barrier layers that are alternately stacked, the well layers includes at least one first well layer, at least one second well layer, and third well layers that have different indium concentrations. The first well layer has the largest indium concentration, and the third well layers have the smallest indium concentration. Three of well layers that are closest to the P-type semiconductor layer are the third well layers, and the first well layer is closer to the N-type semiconductor layer than the P-type semiconductor layer.
    Type: Application
    Filed: February 1, 2022
    Publication date: May 19, 2022
    Inventors: BEN-JIE FAN, JING-QIONG ZHANG, YI-QUN LI, HUNG-CHIH YANG, TSUNG-CHIEH LIN, HO-CHIEN CHEN, SHUEN-TA TENG, CHENG-CHANG HSIEH
  • Patent number: 11336215
    Abstract: A display including a supporting stand and a display panel is provided. The supporting stand has a rotating assembly, a drive motor, and a microcontroller. The display panel has a computing device. The drive motor is connected to the rotating assembly for driving the rotating assembly to rotate. The microcontroller is coupled to the drive motor for controlling the drive motor. The display panel is disposed on the rotating assembly. The computing device is coupled to the microcontroller. The computing device is configured to read an image. The computing device transmits a signal to the microcontroller based on an orientation of the image being portrait or landscape so that the microcontroller switches on the drive motor and the rotating assembly drives the display panel to rotate relative to the supporting stand for switching a rotating position of the display panel to a portrait mode or a landscape mode.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: May 17, 2022
    Assignee: PEGATRON CORPORATION
    Inventors: Tai-Jung Huang, Pei-Chin Wang, Chien-Sheng Lo, Yu-Lin Fang, Yu-Ting Tsai
  • Publication number: 20220137518
    Abstract: An immersion lithography system includes an immersion hood, wherein the immersion hood includes a lens system. The immersion lithography system further includes a wafer stage, wherein the wafer stage is moveable relative to the immersion hood, and the wafer stage includes an area for receiving a wafer. The immersion lithography system further includes a first particle capture area on the wafer stage outside of the area for receiving the wafer, wherein the first particle capture area includes silicon, silicon nitride oxide or a photoresist material.
    Type: Application
    Filed: October 29, 2020
    Publication date: May 5, 2022
    Inventors: Yung-Yao LEE, Wei Chih LIN, Chih Chien LIN
  • Publication number: 20220139542
    Abstract: According to one or more aspects of the present disclosure a wearable oral device is provided. The wearable oral device may include a mouthpiece; a bone conduction component; and a processing device. The processing device may detect one or more user interactions by a first user with the wearable oral device; and perform one or more operations in view of the one or more user interactions. The one or more user interactions may include a user interaction by the first user with the mouthpiece. The one or more operations may include presenting a content item via the bone conduction component of the wearable oral device. The content item may include audio content. In some embodiments, the content item comprises a voice message from a second user.
    Type: Application
    Filed: April 28, 2021
    Publication date: May 5, 2022
    Applicant: 5th Social Media Technology Inc.
    Inventors: Xiao Liu, Eric Yuansuo Schee, Chien Lin, Vincent Chen