Patents by Inventor Chien Ling Hwang

Chien Ling Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD OF MAKING A CONDUCTIVE PILLAR BUMP WITH NON-METAL SIDEWALL PROTECTION STRUCTURE
    Publication number: 20140335687
    Abstract: A method of making a semiconductor device includes forming an under bump metallurgy (UBM) layer over a substrate, the UBM layer comprising sidewalls and a surface region. The method further includes forming a conductive pillar over the UBM layer, the conductive pillar includes sidewalls, wherein the conductive pillar exposes the surface region of the UBM layer. The method further includes forming a non-metal protective structure over the sidewalls of the conductive pillar, wherein the non-metal protective structure contacts the surface region of the UBM layer, and the non-metal protective structure exposes the sidewalls of the UBM layer.
    Type: Application
    Filed: July 28, 2014
    Publication date: November 13, 2014
    Inventors: Yi-Wen WU, Cheng-Chung LIN, Chien Ling HWANG, Chung-Shi LIU
  • WAFER LEVEL TRANSFER MOLDING AND APPARATUS FOR PERFORMING THE SAME
    Publication number: 20140291881
    Abstract: A method includes placing a package structure into a mold chase, with top surfaces of device dies in the package structure contacting a release film in the mold chase. A molding compound is injected into an inner space of the mold chase through an injection port, with the injection port on a side of the mold chase. During the injection of the molding compound, a venting step is performed through a first venting port and a second venting port of the mold chase. The first venting port has a first flow rate, and the second port has a second flow rate different from the first flow rate.
    Type: Application
    Filed: June 12, 2014
    Publication date: October 2, 2014
    Inventors: Bor-Ping Jang, Yeong-Jyh Lin, Chien Ling Hwang, Chung-Shi Liu, Meng-Tse Chen, Ming-Da Cheng, Chen-Hua Yu
  • Cu pillar bump with non-metal sidewall protection structure
    Patent number: 8841766
    Abstract: Sidewall protection processes are provided for Cu pillar bump technology, in which a protection structure on the sidewalls of the Cu pillar bump is formed of at least one of non-metal material layers, for example a dielectric material layer, a polymer material layer, or combinations thereof.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: September 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Yi-Wen Wu, Chun-Chieh Wang, Chung-Shi Liu
  • Fan-Out Interconnect Structure and Method for Forming Same
    Publication number: 20140264930
    Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.
    Type: Application
    Filed: July 9, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yen-Chang Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu, Chien Ling Hwang, Chih-Wei Lin, Chen-Shien Chen
  • Apparatus and method of separating wafer from carrier
    Patent number: 8834662
    Abstract: A method of separating a wafer from a carrier includes placing a wafer assembly on a platform. The wafer assembly includes the wafer, the carrier, and a layer of wax between the wafer and the carrier. A wafer frame is mounted on the wafer of the wafer assembly. The layer of wax is softened. The wafer and the wafer frame mounted thereon are separated, by a first robot arm, from the carrier.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Lin-Wei Wang, Chung-Shi Liu
  • Wafer's ambiance control
    Patent number: 8827695
    Abstract: A semiconductor manufacturing system, an interface system, a carrier, and a method for providing an ambient controlled environment is disclosed. The semiconductor manufacturing system comprises a plurality of process chambers; at least one interface system, wherein the interface system includes a first ambient control element; at least one carrier, wherein the carrier comprises a second ambient control element; and a control module coupled to the plurality of process chambers, the at least one interface system, and the at least one carrier.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Li Hsiao, Chen-Hua Yu, Jean Wang, Ming-che Ho, Chien-Ling Hwang, Jui-Pin Hung
  • Copper pillar bump with non-metal sidewall protection structure and method of making the same
    Patent number: 8823167
    Abstract: This description relates to an integrated circuit device including a conductive pillar formed over a substrate. The conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer between the substrate and the conductive pillar. The UBM layer has a surface region. The integrated circuit device further includes a protection structure on the sidewall surface of the conductive pillar and the surface region of the UBM layer. The protection structure is formed of a non-metal material.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Wen Wu, Cheng-Chung Lin, Chien Ling Hwang, Chung-Shi Liu
  • Pillar bumps and process for making same
    Patent number: 8823166
    Abstract: Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chung Lin, Chung-Shi Liu, Meng-Wei Chou, Kuo Cheng Lin, Wen-Hsiung Lu, Chien Ling Hwang, Ying-Jui Huang, De-Yuan Lu
  • METHOD AND SYSTEM FOR MANUFACTURING SEMICONDUCTOR DEVICE
    Publication number: 20140154871
    Abstract: A method for manufacturing a semiconductor device is provided. The method contains steps of providing the semiconductor device including a working area; directing a medium flow onto the working area; configuring a lens in contact with the medium flow; and directing a laser beam to the working area through the lens and the medium flow. A laser processing for manufacturing a semiconductor device is also provided.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 5, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Ling Hwang, Bor-Ping Jang, Yi-Li Hsiao, Hsin-Hung Liao, Chung-Shi Liu
  • Semiconductor Device with Copper-Tin Compound on Copper Connector
    Publication number: 20140131863
    Abstract: An embodiment is a method for forming a semiconductor assembly including cleaning a connector including copper formed on a substrate, applying cold tin to the connector, applying hot tin to the connector, and spin rinsing and drying the connector.
    Type: Application
    Filed: January 16, 2014
    Publication date: May 15, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Ling Hwang, Yi-Li Hsiao, Chung-Shi Liu
  • Package assembly cleaning process using vaporized solvent
    Patent number: 8702871
    Abstract: A method includes generating a solvent-containing vapor that contains a solvent. The solvent-containing vapor is conducted to a package assembly to clean the package assembly. The solvent-containing vapor condenses to form a liquid on a surface of the package assembly, and flows off from the surface of the package assembly.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Li Hsiao, Bor-Ping Jang, Kuei-Wei Huang, Lin-Wei Wang, Chien Ling Hwang, Chung-Shi Liu
  • Apparatus for Holding Semiconductor Wafers
    Publication number: 20140097175
    Abstract: Apparatus for holding semiconductor wafers during semiconductor manufacturing processes are disclosed. In one embodiment, the apparatus comprises a heat-conductive layer disposed on a supporting base. The apparatus also comprises a plurality of holes formed through the heat-conductive layer and the supporting base. The apparatus further comprises a plurality of heat-conductive lift pins that extend through the holes over the heat-conductive layer at the top end, and make a direct contact with a wafer substrate. The heat-conductive layer and the lift pins are connected to a heating circuit.
    Type: Application
    Filed: December 9, 2013
    Publication date: April 10, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Chien Ling Hwang
  • Method for reducing voids in a copper-tin interface and structure formed thereby
    Patent number: 8679591
    Abstract: An embodiment is a method for forming a semiconductor assembly including cleaning a connector including copper formed on a substrate, applying cold tin to the connector, applying hot tin to the connector, and spin rinsing and drying the connector.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: March 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Yi-Li Hsiao, Chung-Shi Liu
  • In-situ accuracy control in flux dipping
    Patent number: 8668131
    Abstract: A flux dipping apparatus includes a flux plate having a top surface; and a dipping cavity in the flux plate and recessed from the top surface. A flux leveler is disposed over the flux plate and configured to move parallel to the top surface. A piezoelectric actuator is configured to adjust a distance between the flux leveler and the top surface in response to a controlling voltage applied to electrodes of the first piezoelectric actuator.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: March 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Li Hsiao, Chen-Hua Yu, Chung-Shi Liu, Chien Ling Hwang
  • Methods for Forming Apparatus for Stud Bump Formation
    Publication number: 20140061153
    Abstract: An apparatus used for forming stud bumps may be formed by providing a first clamp plate comprising a clamping surface, forming a notcher on the clamping surface, and forming a contact stopper on the clamping surface. The apparatus may include a clamp that includes at least two opposing plates, and at least one of the opposing plates includes a protruding feature that intersects the wire when the wire is clamped forming a first notch in the wire. The method for forming stud bumps includes bonding wire to a bonding surface, releasing the wire from the clamp, passing the wire a notch pitch distance through the clamp, clamping the wire with the clamp forming a second notch in the wire, and breaking the wire leaving a bonded portion of the wire on the bonding surface.
    Type: Application
    Filed: August 6, 2013
    Publication date: March 6, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yeong-Jyh Lin, Hsin-Hung Liao, Chien Ling Hwang, Chung-Shi Liu, Mirng-Ji Lii, Chen-Hua Yu, Yi-Li Hsiao
  • Innovative Multi-Purpose Dipping Plate
    Publication number: 20140048586
    Abstract: The present disclosure is directed to an apparatus for the application of soldering flux to a semiconductor workpiece. In some embodiments the apparatus comprises a dipping plate having a reservoir which is adapted to containing different depths of flux material. In some embodiments, the reservoir comprises at least two landing regions having sidewalls which form first and second dipping zones. The disclosed apparatus can allow dipping of the semiconductor workpiece in different depths of soldering flux without the necessity for changing dipping plates.
    Type: Application
    Filed: August 15, 2012
    Publication date: February 20, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bor-Ping Jang, Lin-Wei Wang, Ying-Jui Huang, Yi-Li Hsiao, Chien Ling Hwang, Chung-Shi Liu
  • Apparatus for holding semiconductor wafers
    Patent number: 8652260
    Abstract: Apparatus for holding semiconductor wafers during semiconductor manufacturing processes are disclosed. In one embodiment, the apparatus comprises a heat-conductive layer disposed on a supporting base. The apparatus also comprises a plurality of holes formed through the heat-conductive layer and the supporting base. The apparatus further comprises a plurality of heat-conductive lift pins that extend through the holes over the heat-conductive layer at the top end, and make a direct contact with a wafer substrate. The heat-conductive layer and the lift pins are connected to a heating circuit.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: February 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chien Ling Hwang
  • Pick-and-Place Tool for Packaging Process
    Publication number: 20140030849
    Abstract: An apparatus includes a guide ring, and a bond head installed on the guide ring. The bond head is configured to move in loops along the guide ring.
    Type: Application
    Filed: September 27, 2013
    Publication date: January 30, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Ying-Jui Huang, Yi-Li Hsiao
  • Conductive feature for semiconductor substrate and method of manufacture
    Patent number: 8587119
    Abstract: An embodiment of the disclosure includes a conductive feature on a semiconductor die. A substrate is provided. A bond pad is formed over the substrate. The bond pad has a first width. A polyimide layer is formed over the substrate and the bond pad. The polyimide layer has a first opening over the bond pad with a second width. A silicon-based protection layer overlies the polyimide layer. The silicon-based protection layer has a second opening over the bond pad with a third width. The first opening and the second opening form a combined opening having sidewalls to expose a portion of the bond pad. A UBM layer is formed over the sidewalls of combined opening to contact the exposed portion of the bond pad. A conductive feature overlies the UBM layer.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: November 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Ling Hwang, Yi-Wen Wu, Chung-Shi Liu
  • METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THROUGH SILICON PLUGS
    Publication number: 20130302979
    Abstract: A method of making a semiconductor device, the method includes forming a first opening and a second opening in a substrate. The method further includes forming a conductive material in the first opening and in the second opening, the conductive material comprising a joined portion where the conductive material in the first opening and the conductive material in the second opening are electrically and thermally connected together at a first surface of the substrate. The method further includes reducing a thickness of the substrate from a second surface of the substrate, opposite the first surface, to expose the conductive material in the first opening and the conductive material in the second opening. The method further includes connecting a device to the second surface of the substrate.
    Type: Application
    Filed: July 15, 2013
    Publication date: November 14, 2013
    Inventors: Chen-Hua YU, Hung-Pin CHANG, Yung-Chi LIN, Chia-Lin YU, Jui-Pin HUNG, Chien Ling HWANG