Patents by Inventor Chien Ling Hwang

Chien Ling Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CHIP PACKAGES AND METHODS OF MANUFACTURE THEREOF
    Publication number: 20160064367
    Abstract: Chip packages and methods of manufacture thereof are described. In an embodiment, a method for manufacturing a chip package may include: providing a support structure including: a base; and a stage pivotably attached to the base, the stage having a surface facing away from the base; attaching a first die having at least one second die disposed thereon to the surface of the stage; pivotably tilting the stage; and after the pivotably tilting, dispensing an underfill over the first die and adjacent to the least one second die, the underfill flowing through a first standoff gap disposed between the first die and the at least one second die.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 3, 2016
    Inventors: Chien Ling Hwang, Pei-Hsuan Lee, Ying-Jui Huang, Yeong-Jyh Lin, Chung-Shi Liu
  • Copper pillar bump with cobalt-containing sidewall protection layer
    Patent number: 9275965
    Abstract: A method of forming an integrated circuit device comprises forming a metal pillar over a semiconductor substrate. The method also comprises forming a solder layer over the metal pillar. The method further comprises forming a metallization layer comprising a cobalt (Co) element, the metallization layer covering the metal pillar and the solder layer. The method additionally comprises thermally reflowing the solder layer to form a solder bump, driving the Co element of the metallization layer into the solder bump. The method also comprises oxidizing the metallization layer to form a metal oxide layer on a sidewall surface of the metal pillar.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: March 1, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Ling Hwang, Zheng-Yi Lim, Chung-Shi Liu
  • Via structure for packaging and a method of forming
    Patent number: 9263302
    Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che Ho, Yi-Wen Wu, Chien Ling Hwang, Hung-Jui Kuo, Chung-Shi Liu
  • Semiconductor wafer device
    Patent number: 9236351
    Abstract: A semiconductor device includes a carrier, several dies disposed on a surface of the carrier and several scribing lines defined on the surface of the carrier. The scribing lines include several continuous lines along a first direction and several discontinuous lines along a second direction. Further, a method of dies singulation includes providing a carrier, disposing several dies on a surface of the carrier according to several scribing lines including several continuous lines along a first direction and several discontinuous lines along a second direction, cutting the carrier according to the continuous lines along the first direction, and cutting the carrier according to the discontinuous lines along the second direction.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: January 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Bor-Ping Jang, Chien Ling Hwang, Hsin-Hung Liao, Yeong-Jyh Lin
  • METHOD AND SYSTEM FOR THINNING WAFER THEREOF
    Publication number: 20150371860
    Abstract: A method for thinning a wafer is provided. The method includes placing a wafer on a support assembly and securing an etching mask to a backside of the wafer. The etching mask covers a peripheral portion of the wafer. The method further includes performing a wet etching process on the backside of the wafer to form a thinned wafer, and the thinned wafer includes peripheral portions having a first thickness and a central portion having a second thickness smaller than the first thickness. A system for forming the thinned wafer is also provided.
    Type: Application
    Filed: September 1, 2015
    Publication date: December 24, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien Ling HWANG, Bor-Ping JANG, Hsin-Hung LIAO, Chung-Shi LIU
  • WAFER-LEVEL MOLDING CHASE DESIGN
    Publication number: 20150364456
    Abstract: An apparatus includes a mold chase, which includes a top portion and an edge ring having a ring-shape. The edge ring is underlying and connected to an edge of the top portion. The edge ring has an injection port and a venting port. A molding guide kit is configured to be inserted into the injection port. The molding guide kit includes a front sidewall having a curved front edge.
    Type: Application
    Filed: June 12, 2014
    Publication date: December 17, 2015
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Hui-Min Huang, Chih-Fan Huang, Ming-Da Cheng, Meng-Tse Chen, Bor-Ping Jang, Chien Ling Hwang
  • Pick-and-Place Tool for Packaging Process
    Publication number: 20150333033
    Abstract: A method includes moving a first bond head along a first guide apparatus for a first loop. The first guide apparatus is configured in a ring shape. The method also includes picking up a first die using the first bond head during the first loop, and aligning the first die with a first package substrate. The aligning the first die with the first package substrate includes moving the first package substrate in a first direction and a second direction. The first direction and the second direction are contained in a first plane parallel to the first loop. The method further includes placing the first die over the first package substrate during the first loop.
    Type: Application
    Filed: July 28, 2015
    Publication date: November 19, 2015
    Inventors: Chien Ling Hwang, Ying-Jui Huang, Yi-Li Hsiao
  • METHOD OF MAKING A PILLAR STRUCTURE HAVING A NON-METAL SIDEWALL PROTECTION STRUCTURE AND INTEGRATED CIRCUIT INCLUDING THE SAME
    Publication number: 20150325546
    Abstract: An integrated circuit device includes a semiconductor substrate; and a pad region over the semiconductor substrate. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer over the pad region. The integrated circuit device further includes a conductive pillar on the UBM layer, wherein the conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes a protection structure over the sidewall surface of the conductive pillar, wherein sidewalls of the UBM layer are substantially free of the protection structure, and the protection structure is a non-metal material.
    Type: Application
    Filed: July 21, 2015
    Publication date: November 12, 2015
    Inventors: Chien Ling HWANG, Yi-Wen WU, Chun-Chieh WANG, Chung-Shi LIU
  • 3D INTEGRATED CIRCUIT PACKAGE PROCESSING WITH PANEL TYPE LID
    Publication number: 20150262973
    Abstract: Presented herein is a package comprising a carrier device of a device stack and at least one top device of the device stack mounted on a first side of the carrier device. A lid is mounted on the first side of the carrier device, with a first portion of the lid attached to the carrier device and a second portion of the lid extending past and overhanging a respective edge of the carrier device. The lid comprises a recess disposed in a first side, and the at least one top device is disposed within the recess. A thermal interface material disposed on the top device and contacts a surface of the recess.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 17, 2015
    Inventors: Tsung-Ding Wang, Han-Ping Pu, Kim Hong Chen, Jung Wei Cheng, Chien Ling Hwang, Hsin-Yu Pan
  • Dam for Three-Dimensional Integrated Circuit
    Publication number: 20150262900
    Abstract: An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 17, 2015
    Inventors: Tsung-Ding Wang, An-Jhih Su, Chien Ling Hwang, Jung Wei Cheng, Hsin-Yu Pan, Chen-Hua Yu
  • Methods for Controlling Warpage in Packaging
    Publication number: 20150262845
    Abstract: A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages.
    Type: Application
    Filed: May 29, 2015
    Publication date: September 17, 2015
    Inventors: Chien Ling Hwang, Bor-Ping Jang, Hsin-Hung Liao, Yeong-Jyh Lin, Hsiao-Chung Liang, Chung-Shi Liu
  • Method of making a pillar structure having a non-metal sidewall protection structure
    Patent number: 9136167
    Abstract: A method of making a pillar structure includes forming a first under-bump-metallurgy (UBM) layer formed on a pad region of a substrate, wherein the first UBM layer includes sidewalls. The method further includes forming a second UBM layer on the first UBM layer, wherein the second UBM layer includes a sidewall surface, an area of the first UBM layer is greater than an area of the second UBM layer. The method further includes forming a copper-containing pillar on the second UBM layer, wherein the copper-containing pillar includes a sidewall surface and a top surface. The method further includes forming a protection structure on the sidewall surface of the copper-containing pillar and on an entirety of the sidewall surface of the second UBM layer, wherein the protection structure does not cover the sidewalls of the first UBM layer, and the protection structure is a non-metal material.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: September 15, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Ling Hwang, Yi-Wen Wu, Chun-Chieh Wang, Chung-Shi Liu
  • Method and system for thinning wafer thereof
    Patent number: 9129899
    Abstract: Embodiments of a method for thinning a wafer are provided. The method includes placing a wafer on a support assembly and securing an etching mask to a backside of the wafer. The etching mask covers a peripheral portion of the wafer. The method further includes performing a wet etching process on the backside of the wafer to form a thinned wafer, and the thinned wafer includes peripheral portions having a first thickness and a central portion having a second thickness smaller than the first thickness. Embodiments of system for forming the thinned wafer are also provided.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: September 8, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling Hwang, Bor-Ping Jang, Hsin-Hung Liao, Chung-Shi Liu
  • Via Structure For Packaging And A Method Of Forming
    Publication number: 20150243531
    Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.
    Type: Application
    Filed: February 21, 2014
    Publication date: August 27, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Che Ho, Yi-Wen Wu, Chien Ling Hwang, Hung-Jui Kuo, Chung-Shi Liu
  • Methods for Stud Bump Formation and Apparatus for Performing the Same
    Publication number: 20150235975
    Abstract: An apparatus includes a spool configured to supply a wire, a cutting device configured to form a notch in the wire, and a capillary configured to bond the wire and to form a stud bump. The apparatus is further configured to pull the wire to break at the notch, with a tail region attached to the stud bump.
    Type: Application
    Filed: May 4, 2015
    Publication date: August 20, 2015
    Inventors: Chien Ling Hwang, Yeong-Jyh Lin, Yi-Li Hsiao, Ming-Da Cheng, Tsai-Tsung Tsai, Chung-Shi Liu, Mirng-Ji Lii, Chen-Hua Yu
  • METHOD OF FORMING CU PILLAR BUMP WITH NON-METAL SIDEWALL SPACER AND METAL TOP CAP
    Publication number: 20150228533
    Abstract: A method of forming an integrated circuit device includes forming a conductive element over a substrate, wherein the conductive element is over an under bump metallurgy (UBM) layer, and the UBM layer comprises a first UBM layer and a second UBM layer over the first UBM layer. The method further includes etching the second UBM layer to expose a portion of the first UBM layer beyond a periphery of the conductive element. The method further includes forming a protection layer over sidewalls of the conductive element, over sidewalls of the second UBM layer and over a top surface of the first UBM layer. The method further includes etching the first UBM layer to remove a portion of the first UBM layer. The method further includes forming a cap layer over a top surface of the conductive element.
    Type: Application
    Filed: April 23, 2015
    Publication date: August 13, 2015
    Inventors: Chien Ling HWANG, Hui-Jung TSAI, Yi-Wen WU, Chung-Shi LIU
  • Pick-and-place tool for packaging process
    Patent number: 9105760
    Abstract: An apparatus includes a guide ring, and a bond head installed on the guide ring. The bond head is configured to move in loops along the guide ring. The bond head is configured to pick up dies and place the dies during the loops.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: August 11, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Ying-Jui Huang, Yi-Li Hsiao
  • Methods for controlling warpage in packaging
    Patent number: 9093337
    Abstract: A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: July 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Bor-Ping Jang, Hsin-Hung Liao, Yeong-Jyh Lin, Hsiao-Chung Liang, Chung-Shi Liu
  • Method and system for manufacturing semiconductor device
    Patent number: 9085049
    Abstract: A method for manufacturing a semiconductor device is provided. The method contains steps of providing the semiconductor device including a working area; directing a medium flow onto the working area; configuring a lens in contact with the medium flow; and directing a laser beam to the working area through the lens and the medium flow. A laser processing for manufacturing a semiconductor device is also provided.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: July 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Ling Hwang, Bor-Ping Jang, Yi-Li Hsiao, Hsin-Hung Liao, Chung-Shi Liu
  • Packaging through Pre-Formed Metal Pins
    Publication number: 20150200171
    Abstract: A package includes first package component and a second package component. The first package component includes a first electrical connector at a surface of the first package component, and a first solder region on a surface of the first electrical connector. The second package component includes a second electrical connector at a surface of the second package component, and a second solder region on a surface of the second electrical connector. A metal pin has a first end bonded to the first solder region, and a second end bonded to the second solder region.
    Type: Application
    Filed: January 13, 2014
    Publication date: July 16, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Chien Ling Hwang, Yeong-Jyh Lin