Abstract: An integrated circuit device includes a Cu pillar and a solder layer overlying the Cu pillar. A Co-containing metallization layer is formed to cover the Cu pillar and the solder layer, and then a thermally reflow process is performed to form a solder bump and drive the Co element into the solder bump. Next, an oxidation process is performed to form a cobalt oxide layer on the sidewall surface of the Cu pillar.

Abstract: The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns.

Abstract: A mold includes a top portion, and an edge ring having a ring-shape. The edge ring is underlying and connected to edges of the top portion. The edge ring includes air vents. The edge ring further encircles the inner space under the top portion of the mold. A plurality of injection ports is connected to the inner space of the mold. The plurality of injection ports is substantially aligned to a straight line crossing a center of the top portion of the mold. The plurality of injection ports has different sizes.

Abstract: An apparatus includes a spool configured to supply a wire, a cutting device configured to form a notch in the wire, and a capillary configured to bond the wire and to form a stud bump. The apparatus is further configured to pull the wire to break at the notch, with a tail region attached to the stud bump.

Abstract: A bump has a non-metal sidewall spacer on a lower sidewall portion of Cu pillar, and a metal top cap on a top surface and an upper sidewall portion of the Cu pillar. The metal top cap is formed by an electroless or immersion plating technique after the non-metal sidewall spacer formation.

Abstract: An apparatus used for forming stud bumps may be formed by providing a first clamp plate comprising a clamping surface, forming a notcher on the clamping surface, and forming a contact stopper on the clamping surface. The apparatus may include a clamp that includes at least two opposing plates, and at least one of the opposing plates includes a protruding feature that intersects the wire when the wire is clamped forming a first notch in the wire. The method for forming stud bumps includes bonding wire to a bonding surface, releasing the wire from the clamp, passing the wire a notch pitch distance through the clamp, clamping the wire with the clamp forming a second notch in the wire, and breaking the wire leaving a bonded portion of the wire on the bonding surface.

Abstract: A semiconductor device includes a carrier, several dies disposed on a surface of the carrier and several scribing lines defined on the surface of the carrier. The scribing lines include several continuous lines along a first direction and several discontinuous lines along a second direction. Further, a method of dies singulation includes providing a carrier, disposing several dies on a surface of the carrier according to several scribing lines including several continuous lines along a first direction and several discontinuous lines along a second direction, cutting the carrier according to the continuous lines along the first direction, and cutting the carrier according to the discontinuous lines along the second direction.

Abstract: A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages.

Abstract: A semiconductor device includes a substrate and a first conductive pad on a top surface of the substrate. The semiconductor device further includes a boundary structure on the top surface of the substrate around the conductive pad.

Abstract: A mold includes a top portion, and an edge ring having a ring-shape. The edge ring is underlying and connected to edges of the top portion. The edge ring includes air vents. The edge ring further encircles the inner space under the top portion of the mold. A plurality of injection ports is connected to the inner space of the mold. The plurality of injection ports is substantially aligned to a straight line crossing a center of the top portion of the mold. The plurality of injection ports has different sizes.

Abstract: The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns.

Abstract: A method for cutting a semiconductor wafer into semiconductor chips that reduces defects at the semiconductor chip corners. The method includes a pre-cutting processing step of trimming the semiconductor chip corners so that mechanical stress is reduced at the corners. The method includes dicing channels on a semiconductor wafer thereby defining the geometrical shape of one of the semiconductor chips, modifying the corners of the one of the semiconductor chips, and cutting the semiconductor wafer to separate the one of the semiconductor chips from other semiconductor chips.

Abstract: Embodiments of a method for thinning a wafer are provided. The method includes placing a wafer on a support assembly and securing an etching mask to a backside of the wafer. The etching mask covers a peripheral portion of the wafer. The method further includes performing a wet etching process on the backside of the wafer to form a thinned wafer, and the thinned wafer includes peripheral portions having a first thickness and a central portion having a second thickness smaller than the first thickness. Embodiments of system for forming the thinned wafer are also provided.

Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.

Abstract: An apparatus used for forming stud bumps may be formed by providing a first clamp plate comprising a clamping surface, forming a notcher on the clamping surface, and forming a contact stopper on the clamping surface. The apparatus may include a clamp that includes at least two opposing plates, and at least one of the opposing plates includes a protruding feature that intersects the wire when the wire is clamped forming a first notch in the wire. The method for forming stud bumps includes bonding wire to a bonding surface, releasing the wire from the clamp, passing the wire a notch pitch distance through the clamp, clamping the wire with the clamp forming a second notch in the wire, and breaking the wire leaving a bonded portion of the wire on the bonding surface.

Abstract: A method of making a pillar structure includes forming a first under-bump-metallurgy (UBM) layer formed on a pad region of a substrate, wherein the first UBM layer includes sidewalls. The method further includes forming a second UBM layer on the first UBM layer, wherein the second UBM layer includes a sidewall surface, an area of the first UBM layer is greater than an area of the second UBM layer. The method further includes forming a copper-containing pillar on the second UBM layer, wherein the copper-containing pillar includes a sidewall surface and a top surface. The method further includes forming a protection structure on the sidewall surface of the copper-containing pillar and on an entirety of the sidewall surface of the second UBM layer, wherein the protection structure does not cover the sidewalls of the first UBM layer, and the protection structure is a non-metal material.

Abstract: An apparatus for separating a wafer from a carrier includes a platform having an upper surface, a tape feeding unit, a first robot arm, and a controller coupled to the platform. The controller is configured to mount a wafer frame, by using the tape feeding unit, on a wafer of a wafer assembly on the upper surface of the platform. The wafer assembly includes the wafer, a carrier, and a layer of wax between the wafer and the carrier. The controller is also configured to heat the upper surface of the platform to a predetermined temperature and separate, by the first robot arm, the wafer and the wafer frame mounted thereon from the carrier.

Abstract: Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.

Abstract: A method of forming an integrated circuit device comprises forming a metal pillar over a semiconductor substrate. The method also comprises forming a solder layer over the metal pillar. The method further comprises forming a metallization layer comprising a cobalt (Co) element, the metallization layer covering the metal pillar and the solder layer. The method additionally comprises thermally reflowing the solder layer to form a solder bump, driving the Co element of the metallization layer into the solder bump. The method also comprises oxidizing the metallization layer to form a metal oxide layer on a sidewall surface of the metal pillar.

Abstract: A method of making a semiconductor device includes forming an under bump metallurgy (UBM) layer over a substrate, the UBM layer comprising sidewalls and a surface region. The method further includes forming a conductive pillar over the UBM layer, the conductive pillar includes sidewalls, wherein the conductive pillar exposes the surface region of the UBM layer. The method further includes forming a non-metal protective structure over the sidewalls of the conductive pillar, wherein the non-metal protective structure contacts the surface region of the UBM layer, and the non-metal protective structure exposes the sidewalls of the UBM layer.