Patents by Inventor Chien Ling Hwang

Chien Ling Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cu pillar bump with L-shaped non-metal sidewall protection structure
    Patent number: 9524945
    Abstract: An L-shaped sidewall protection process is used for Cu pillar bump technology. The L-shaped sidewall protection structure is formed of at least one of non-metal material layers, for example a dielectric material layer, a polymer material layer or combinations thereof.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: December 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Ling Hwang, Yi-Wen Wu, Chung-Shi Liu
  • Packaging through Pre-Formed Metal Pins
    Publication number: 20160343681
    Abstract: A package includes first package component and a second package component. The first package component includes a first electrical connector at a surface of the first package component, and a first solder region on a surface of the first electrical connector. The second package component includes a second electrical connector at a surface of the second package component, and a second solder region on a surface of the second electrical connector. A metal pin has a first end bonded to the first solder region, and a second end bonded to the second solder region.
    Type: Application
    Filed: August 2, 2016
    Publication date: November 24, 2016
    Inventors: Chen-Hua Yu, Chien Ling Hwang, Yeong-Jyh Lin
  • Methods for forming apparatus for stud bump formation
    Patent number: 9498851
    Abstract: An apparatus used for forming stud bumps may be formed by providing a first clamp plate comprising a clamping surface, forming a notcher on the clamping surface, and forming a contact stopper on the clamping surface. The apparatus may include a clamp that includes at least two opposing plates, and at least one of the opposing plates includes a protruding feature that intersects the wire when the wire is clamped forming a first notch in the wire. The method for forming stud bumps includes bonding wire to a bonding surface, releasing the wire from the clamp, passing the wire a notch pitch distance through the clamp, clamping the wire with the clamp forming a second notch in the wire, and breaking the wire leaving a bonded portion of the wire on the bonding surface.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yeong-Jyh Lin, Hsin-Hung Liao, Chien Ling Hwang, Yi-Li Hsiao, Chung-Shi Liu, Mirng-Ji Lii, Chen-Hua Yu
  • 3D integrated circuit package processing with panel type lid
    Patent number: 9502383
    Abstract: Presented herein is a package comprising a carrier device of a device stack and at least one top device of the device stack mounted on a first side of the carrier device. A lid is mounted on the first side of the carrier device, with a first portion of the lid attached to the carrier device and a second portion of the lid extending past and overhanging a respective edge of the carrier device. The lid comprises a recess disposed in a first side, and the at least one top device is disposed within the recess. A thermal interface material disposed on the top device and contacts a surface of the recess.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Ding Wang, Han-Ping Pu, Kim Hong Chen, Jung Wei Cheng, Chien Ling Hwang, Hsin-Yu Pan
  • Methods for controlling warpage in packaging
    Patent number: 9484226
    Abstract: A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: November 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Bor-Ping Jang, Hsin-Hung Liao, Yeong-Jyh Lin, Hsiao-Chung Liang, Chung-Shi Liu
  • Package-on-package structures and methods of manufacture thereof
    Patent number: 9460939
    Abstract: A method for manufacturing a package-on-package structure may include: providing a support structure having a package attached to an inclined surface of the support structure, the package comprising: a first chip package; a second chip package disposed over the first chip package; and a standoff gap between the first chip package and the second chip package, wherein a first side of the package is disposed higher on the inclined surface of the support structure than a second side of the package; and dispensing an underfill into the standoff gap, the underfill flowing through the standoff gap from the first side of the package to the second side of the package.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: October 4, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Hsuan Lee, Chien Ling Hwang, Chung-Shi Liu, Chen-Hua Yu
  • Fan-Out Interconnect Structure and Method for Forming Same
    Publication number: 20160284654
    Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.
    Type: Application
    Filed: June 8, 2016
    Publication date: September 29, 2016
    Inventors: Chen-Hua Yu, Shou-Cheng Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu, Chien Ling Hwang, Chih-Wei Lin, Chen-Shien Chen
  • Pillar bumps and process for making same
    Patent number: 9449931
    Abstract: Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chung Lin, Chung-Shi Liu, Meng-Wei Chou, Kuo Cheng Lin, Wen-Hsiung Lu, Chien Ling Hwang, Ying-Jui Huang, De-Yuan Lu
  • METHOD OF MANUFACTURING MICRO PINS AND ISOLATED CONDUCTIVE MICRO PIN
    Publication number: 20160254239
    Abstract: A method of manufacturing micro pins includes forming a release layer over a substrate. A pattern layer is formed over the release layer, in which the pattern layer has a plurality of openings spaced apart to each other and through the pattern layer. A plurality of micro pins are respectively formed in the openings. The pattern layer and the release layer are removed to obtain the micro pins. An isolated conductive micro pin for connecting one or more components is also provided.
    Type: Application
    Filed: February 26, 2015
    Publication date: September 1, 2016
    Inventors: Ying-Jui HUANG, Chung-Shi LIU, Hsin-Hung LIAO, Chien-Ling HWANG
  • Chip packages and methods of manufacture thereof
    Patent number: 9425179
    Abstract: Chip packages and methods of manufacture thereof are described. In an embodiment, a method for manufacturing a chip package may include: providing a support structure including: a base; and a stage pivotably attached to the base, the stage having a surface facing away from the base; attaching a first die having at least one second die disposed thereon to the surface of the stage; pivotably tilting the stage; and after the pivotably tilting, dispensing an underfill over the first die and adjacent to the least one second die, the underfill flowing through a first standoff gap disposed between the first die and the at least one second die.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Pei-Hsuan Lee, Ying-Jui Huang, Yeong-Jyh Lin, Chung-Shi Liu
  • INTERCONNECT STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE INTERCONNECT STRUCTURE
    Publication number: 20160240451
    Abstract: A semiconductor package includes a carrier, at least and adhesive portion, a plurality of micro pins and a die. The carrier has a first surface and second surface opposite to the first surface. The adhesive portion is disposed on the first surface, and the plurality of the micro pins is disposed in the adhesive portions. The die is disposed on the remaining adhesive portion free of the micro pins.
    Type: Application
    Filed: February 13, 2015
    Publication date: August 18, 2016
    Inventors: Chien-Ling HWANG, Bor-Ping JANG, Chung-Shi LIU, Hsin-Hung LIAO, Ying-Jui HUANG
  • Packaging through pre-formed metal pins
    Patent number: 9418953
    Abstract: A package includes first package component and a second package component. The first package component includes a first electrical connector at a surface of the first package component, and a first solder region on a surface of the first electrical connector. The second package component includes a second electrical connector at a surface of the second package component, and a second solder region on a surface of the second electrical connector. A metal pin has a first end bonded to the first solder region, and a second end bonded to the second solder region.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chien Ling Hwang, Yeong-Jyh Lin
  • METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THROUGH SILICON PLUGS
    Publication number: 20160197014
    Abstract: A method of making a semiconductor device is provided including forming a first opening and a second opening in a first surface of a substrate. A conductive material is formed in the first opening and in the second opening and over the first surface in the first region of the substrate between the openings. A thickness of the substrate may be reduced from a second surface of the substrate, opposite the first surface, to a third surface opposite the first surface which exposes the conductive material in the first opening and the conductive material in the second opening. A light emitting diode (LED) device is connected to the third surface of the substrate.
    Type: Application
    Filed: March 14, 2016
    Publication date: July 7, 2016
    Inventors: Chen-Hua YU, Hung-Pin CHANG, Yung-Chi LIN, Chia-Lin YU, Jui-Pin HUNG, Chien Ling HWANG
  • Fan-out interconnect structure and method for forming same
    Patent number: 9368460
    Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yen-Chang Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu, Chien Ling Hwang, Chih-Wei Lin, Chen-Shien Chen
  • Via Structure For Packaging And A Method Of Forming
    Publication number: 20160155650
    Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.
    Type: Application
    Filed: February 9, 2016
    Publication date: June 2, 2016
    Inventors: Ming-Che Ho, Yi-Wen Wu, Chien Ling Hwang, Hung-Jui Kuo, Chung-Shi Liu
  • PACKAGE-ON-PACKAGE STRUCTURES AND METHODS OF MANUFACTURE THEREOF
    Publication number: 20160148820
    Abstract: A method for manufacturing a package-on-package structure may include: providing a support structure having a package attached to an inclined surface of the support structure, the package comprising: a first chip package; a second chip package disposed over the first chip package; and a standoff gap between the first chip package and the second chip package, wherein a first side of the package is disposed higher on the inclined surface of the support structure than a second side of the package; and dispensing an underfill into the standoff gap, the underfill flowing through the standoff gap from the first side of the package to the second side of the package.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 26, 2016
    Inventors: Pei-Hsuan Lee, Chien Ling Hwang, Chung-Shi Liu, Chen-Hua Yu
  • Semiconductor device with copper-tin compound on copper connector
    Patent number: 9324670
    Abstract: An embodiment is a method for forming a semiconductor assembly including cleaning a connector including copper formed on a substrate, applying cold tin to the connector, applying hot tin to the connector, and spin rinsing and drying the connector.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: April 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Yi-Li Hsiao, Chung-Shi Liu
  • SEMICONDUCTOR WAFER DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20160099165
    Abstract: A method of manufacturing a semiconductor device comprises providing a carrier, disposing a plurality of dies over the carrier along a first direction and a second direction orthogonal to the first direction to arrange the plurality of dies in a plurality of rows, and shifting one of the plurality of rows along the first direction or the second direction in a predetermined distance.
    Type: Application
    Filed: December 14, 2015
    Publication date: April 7, 2016
    Inventors: BOR-PING JANG, CHIEN LING HWANG, HSIN-HUNG LIAO, YEONG-JYH LIN
  • Method of making a conductive pillar bump with non-metal sidewall protection structure
    Patent number: 9287171
    Abstract: A method of making a semiconductor device includes forming an under bump metallurgy (UBM) layer over a substrate, the UBM layer comprising sidewalls and a surface region. The method further includes forming a conductive pillar over the UBM layer, the conductive pillar includes sidewalls, wherein the conductive pillar exposes the surface region of the UBM layer. The method further includes forming a non-metal protective structure over the sidewalls of the conductive pillar, wherein the non-metal protective structure contacts the surface region of the UBM layer, and the non-metal protective structure exposes the sidewalls of the UBM layer.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: March 15, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Wen Wu, Cheng-Chung Lin, Chien Ling Hwang, Chung-Shi Liu
  • Method of manufacturing a semiconductor device including through silicon plugs
    Patent number: 9287440
    Abstract: A method of making a semiconductor device, the method includes forming a first opening and a second opening in a substrate. The method further includes forming a conductive material in the first opening and in the second opening, the conductive material comprising a joined portion where the conductive material in the first opening and the conductive material in the second opening are electrically and thermally connected together at a first surface of the substrate. The method further includes reducing a thickness of the substrate from a second surface of the substrate, opposite the first surface, to expose the conductive material in the first opening and the conductive material in the second opening. The method further includes connecting a device to the second surface of the substrate.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hung-Pin Chang, Yung-Chi Lin, Chia-Lin Yu, Jui-Pin Hung, Chien Ling Hwang