Abstract: A method of making a semiconductor device is provided including forming a first opening and a second opening in a first surface of a substrate. A conductive material is formed in the first opening and in the second opening and over the first surface in the first region of the substrate between the openings. A thickness of the substrate may be reduced from a second surface of the substrate, opposite the first surface, to a third surface opposite the first surface which exposes the conductive material in the first opening and the conductive material in the second opening. A light emitting diode (LED) device is connected to the third surface of the substrate.

Abstract: An apparatus includes a spool configured to supply a wire, a cutting device configured to form a notch in the wire, and a capillary configured to bond the wire and to form a stud bump. The apparatus is further configured to pull the wire to break at the notch, with a tail region attached to the stud bump.

Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.

Abstract: An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

Abstract: A method of manufacturing micro pins includes forming a release layer over a substrate. A pattern layer is formed over the release layer, in which the pattern layer has a plurality of openings spaced apart to each other and through the pattern layer. A plurality of micro pins are respectively formed in the openings. The pattern layer and the release layer are removed to obtain the micro pins. An isolated conductive micro pin for connecting one or more components is also provided.

Abstract: A method of dies singulation includes providing a carrier, disposing a plurality of dies over a surface of the carrier according to a plurality of scribe lines comprising a plurality of continuous lines along a first direction and a plurality of discontinuous lines along a second direction, cutting the carrier according to the plurality of continuous lines along the first direction, and cutting the carrier according to the plurality of discontinuous lines along the second direction.

Abstract: A method of making a semiconductor device is provided including forming a first opening and a second opening in a first surface of a substrate. A conductive material is formed in the first opening and in the second opening and over the first surface in the first region of the substrate between the openings. A thickness of the substrate may be reduced from a second surface of the substrate, opposite the first surface, to a third surface opposite the first surface which exposes the conductive material in the first opening and the conductive material in the second opening. A light emitting diode (LED) device is connected to the third surface of the substrate.

Abstract: A package includes first package component and a second package component. The first package component includes a first electrical connector at a surface of the first package component, and a first solder region on a surface of the first electrical connector. The second package component includes a second electrical connector at a surface of the second package component, and a second solder region on a surface of the second electrical connector. A metal pin has a first end bonded to the first solder region, and a second end bonded to the second solder region.

Abstract: An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

Abstract: An apparatus includes a mold chase, which includes a top portion and an edge ring having a ring-shape. The edge ring is underlying and connected to an edge of the top portion. The edge ring has an injection port and a venting port. A molding guide kit is configured to be inserted into the injection port. The molding guide kit includes a front sidewall having a curved front edge.

Abstract: A mold includes a top portion, and an edge ring having a ring-shape. The edge ring is underlying and connected to edges of the top portion. The edge ring includes air vents. The edge ring further encircles the inner space under the top portion of the mold. A plurality of injection ports is connected to the inner space of the mold. The plurality of injection ports is substantially aligned to a straight line crossing a center of the top portion of the mold. The plurality of injection ports has different sizes.

Abstract: Provided is an integrated fan-out package including a die, a first redistribution circuit structure, a second redistribution circuit structure, a plurality of solder joints, a plurality of conductive posts, and an insulating encapsulation. The first redistribution circuit structure and the second redistribution circuit structure are formed respectively over a back surface and an active surface of the die to sandwich the die. The solder joints are formed aside the die and connected to the first redistribution circuit structure. The conductive posts are formed on the solder joints and connected to the second redistribution circuit structure, and connected to the first redistribution circuit structure through the solder joints. A plurality of sidewalls of the die, a plurality of sidewalls of the conductive posts, and a plurality of sidewalls of the solder joints are encapsulated by the insulating encapsulation. A fabricating process of the integrated fan-out package is also provided.

Abstract: A package structure includes a spiral coil, a redistribution layer (RDL) and a molding material. The molding material fills gaps of the spiral coil. The spiral coil is connected to the RDL. A fan-out package structure includes a spiral coil, an RDL and a die. The spiral coil has a depth-to-width ratio greater than about 2. The RDL is connected to the spiral coil. The die is coupled to the spiral coil through the RDL. A semiconductor packaging method includes: providing a carrier; adhering a spiral coil on the carrier; adhering a die on the carrier; dispensing a molding material on the carrier to fill gaps between the spiral coil and the die; and disposing a redistribution layer (RDL) over the carrier so as to connect the spiral coil with the die.

Abstract: A method includes moving a first bond head along a first guide apparatus for a first loop. The first guide apparatus is configured in a ring shape. The method also includes picking up a first die using the first bond head during the first loop, and aligning the first die with a first package substrate. The aligning the first die with the first package substrate includes moving the first package substrate in a first direction and a second direction. The first direction and the second direction are contained in a first plane parallel to the first loop. The method further includes placing the first die over the first package substrate during the first loop.

Abstract: A method for fabricating an integrated fan-out package is provided. The method includes the following steps. A plurality of conductive posts are placed in apertures of a substrate. A carrier having an adhesive thereon is provided. The conductive posts are transferred to the carrier in a standing orientation by adhering the conductive posts in the apertures to the adhesive. An integrated circuit component is mounted onto the adhesive having the conductive posts adhered thereon. An insulating encapsulation is formed to encapsulate the integrated circuit component and the conductive posts. A redistribution circuit structure is formed on the insulating encapsulation, the integrated circuit component, and the conductive posts, wherein the redistribution circuit structure is electrically connected to the integrated circuit component and the conductive posts. The carrier is removed. At least parts of the adhesive are removed (e.g. patterned or entirely removed) to expose surfaces of the conductive posts.

Abstract: A package includes first package component and a second package component. The first package component includes a first electrical connector at a surface of the first package component, and a first solder region on a surface of the first electrical connector. The second package component includes a second electrical connector at a surface of the second package component, and a second solder region on a surface of the second electrical connector. A metal pin has a first end bonded to the first solder region, and a second end bonded to the second solder region.

Abstract: A method of dies singulation includes providing a carrier, disposing a plurality of dies over a surface of the carrier according to a plurality of scribe lines comprising a plurality of continuous lines along a first direction and a plurality of discontinuous lines along a second direction, cutting the carrier according to the plurality of continuous lines along the first direction, and cutting the carrier according to the plurality of discontinuous lines along the second direction.

Abstract: A method includes placing a package structure into a mold chase, with top surfaces of device dies in the package structure contacting a release film in the mold chase. A molding compound is injected into an inner space of the mold chase through an injection port, with the injection port on a side of the mold chase. During the injection of the molding compound, a venting step is performed through a first venting port and a second venting port of the mold chase. The first venting port has a first flow rate, and the second port has a second flow rate different from the first flow rate.

Abstract: A mold includes a top portion, and an edge ring having a ring-shape. The edge ring is underlying and connected to edges of the top portion. The edge ring includes air vents. The edge ring further encircles the inner space under the top portion of the mold. A plurality of injection ports is connected to the inner space of the mold. The plurality of injection ports is substantially aligned to a straight line crossing a center of the top portion of the mold. The plurality of injection ports has different sizes.

Abstract: Provided is an integrated fan-out package including a die, a first redistribution circuit structure, a second redistribution circuit structure, a plurality of solder joints, a plurality of conductive posts, and an insulating encapsulation. The first redistribution circuit structure and the second redistribution circuit structure are formed respectively over a back surface and an active surface of the die to sandwich the die. The solder joints are formed aside the die and connected to the first redistribution circuit structure. The conductive posts are formed on the solder joints and connected to the second redistribution circuit structure, and connected to the first redistribution circuit structure through the solder joints. A plurality of sidewalls of the die, a plurality of sidewalls of the conductive posts, and a plurality of sidewalls of the solder joints are encapsulated by the insulating encapsulation. A fabricating process of the integrated fan-out package is also provided.