Patents by Inventor Chien-Min Lee

Chien-Min Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230089382
    Abstract: A communication device for handling a reference signal (RS) reporting includes at least one storage device; and at least one processing circuit, coupled to the at least one storage device, wherein the at least one storage device stores instructions, and the at least one processing circuit is configured to execute the instructions of: receiving at least one reference signal (RS) from a network; performing at least one measurement according to the at least one RS, to generate at least one measurement result; selecting an RS from the at least one RS according to the at least one measurement result; and determining whether to report the RS to the network.
    Type: Application
    Filed: August 3, 2022
    Publication date: March 23, 2023
    Applicant: ACER INCORPORATED
    Inventors: Li-Chung Lo, Chien-Min Lee, Jen-Hsien Chen
  • Publication number: 20230071950
    Abstract: Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.
    Type: Application
    Filed: November 6, 2022
    Publication date: March 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Min Lee, Ming-Yuan Song, Yen-Lin Huang, Shy-Jay Lin, Tung-Ying Lee, Xinyu BAO
  • Patent number: 11588107
    Abstract: An IC structure comprises a substrate, a first material layer, a second material layer, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first material layer is disposed on the memory region and the logic region. The second material layer is disposed on the first material layer only at the memory region. The first via structure formed in the first material layer and the second material layer. The memory cell structure is over the first via structure.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: February 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee, Han-Ting Tsai, Jyu-Horng Shieh, Chung-Te Lin
  • Patent number: 11582745
    Abstract: A method for bandwidth part (BWP) operating of a serving cell, adapted to a user equipment (UE) in a first BWP, is provided. The method includes: receiving a signaling; and determining whether to switch to a second BWP from the first BWP according to the signaling.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: February 14, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Wei-Chen Pao, Chien-Min Lee, Jen-Hsien Chen
  • Publication number: 20230042313
    Abstract: A communication device for handling a hybrid automatic repeat request (HARQ) transmission, comprises at least one storage device; and at least one processing circuit, coupled to the at least one storage device, wherein the at least one storage device stores instructions, and the at least one processing circuit is configured to execute the instructions of: receiving a configuration from a network, wherein the configuration comprises a time domain resource allocation (TDRA) table and a set of a plurality of timing values; and receiving a downlink (DL) control information (DCI) from the network, wherein the DCI indicates a row of the TDRA table for at least one physical DL shared channel (PDSCH) reception and indicates a timing value of the set of the plurality of timing values for the HARQ transmission corresponding to the at least one PDSCH reception.
    Type: Application
    Filed: July 21, 2022
    Publication date: February 9, 2023
    Applicant: ACER INCORPORATED
    Inventors: Jen-Hsien Chen, Chien-Min Lee, Li-Chung Lo
  • Publication number: 20230009553
    Abstract: Provided are a package structure and a method of forming the same. The method includes: laterally encapsulating a device die and an interconnect die by a first encapsulant; forming a redistribution layer (RDL) structure on the device die, the interconnect die, and the first encapsulant; bonding a package substrate onto the RDL structure, so that the RDL structure is sandwiched between the package substrate and the device die, the interconnect die, and the first encapsulant; laterally encapsulating the package substrate by a second encapsulant; and bonding a memory die onto the interconnect die, wherein the memory die is electrically connected to the device die through the interconnect die and the RDL structure.
    Type: Application
    Filed: July 8, 2021
    Publication date: January 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yang Yu, Yu-Min Liang, Jiun-Yi Wu, Chien-Hsun Lee
  • Publication number: 20230008498
    Abstract: A communication device for handling physical uplink (UL) shared channel (PUSCH) transmissions, comprises at least one storage device; and at least one processing circuit, coupled to the at least one storage device, wherein the at least one storage device stores instructions, and the at least one processing circuit is configured to execute the instructions of receiving an indicator indicating a plurality of physical uplink (UL) shared channel (PUSCH) repetitions from a network; determining at least one nominal transmission duration for the plurality of PUSCH repetitions; and transmitting the plurality of PUSCH repetitions to the network in the at least one nominal transmission duration according to the indication.
    Type: Application
    Filed: June 22, 2022
    Publication date: January 12, 2023
    Applicant: ACER INCORPORATED
    Inventors: Chien-Min Lee, Jen-Hsien Chen, Li-Chung Lo
  • Publication number: 20220415968
    Abstract: An ovonic threshold switch (OTS) selector and a memory device including the OTS selector is provided. The OTS selector includes a switching layer formed of a GeCTe compound further doped with one or both of nitrogen and silicon, and exhibits improved thermal stability and electrical performance.
    Type: Application
    Filed: February 10, 2022
    Publication date: December 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Min Lee, Cheng-Hsien Wu, Cheng-Chun Chang, Elia Ambrosi, Hengyuan Lee, Ying-Yu Chen, Xinyu BAO, Tung-Ying Lee
  • Patent number: 11538858
    Abstract: Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: December 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Min Lee, Ming-Yuan Song, Yen-Lin Huang, Shy-Jay Lin, Tung-Ying Lee, Xinyu Bao
  • Patent number: 11527476
    Abstract: A semiconductor structure and a method of forming the same are provided. A method includes depositing a dielectric layer over a conductive feature. The dielectric layer is patterned to form an opening therein. The opening exposes a first portion of the conductive feature. A first barrier layer is deposited on a sidewall of the opening. The first portion of the conductive feature remains exposed at the end of depositing the first barrier layer.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-Min Liu, Chia-Pang Kuo, Chien Chung Huang, Chih-Yi Chang, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai
  • Publication number: 20220392796
    Abstract: In an embodiment, a system includes: a cassette comprising a slit opening configured to house a wafer; a blade configured to move the wafer to and from the slit opening by extending into the slit opening, wherein a blade thickness of the blade is at most ? of a height of the slit opening and wherein the blade is configured to secure the wafer within a pocket on the blade that is at least ? of a wafer thickness of the wafer.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 8, 2022
    Inventors: Chien-Chih CHEN, Yao-Min YU, Ching-Ling LEE, Ren-Dou LEE
  • Publication number: 20220392832
    Abstract: A method of forming a semiconductor structure includes the following operations. A first conductive structure is formed on a first side of a first glass carrier. A second glass carrier is bonded to the first conductive structure. Conductive vias are formed to penetrate through the first glass carrier, and the conductive vias are electrically connected to the first conductive structure. A second conductive structure is formed on a second side of the first glass carrier opposite to the first side, and the second conductive structure is electrically connected to the conductive vias.
    Type: Application
    Filed: June 6, 2021
    Publication date: December 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, Yu-Min Liang, Tsung-Ding Wang, Jiun-Yi Wu, Chien-Hsun Lee
  • Patent number: 11522313
    Abstract: A waterproof connector disposed on a circuit board of an electronic device and inserted with a housing of the electronic device is provided. The waterproof connector includes a connector and a waterproof covering member. The connector is disposed on the circuit board, and the waterproof covering member covers the connector and a part of the circuit board. An outer surface of the waterproof covering member has multiple ribs, and the ribs contact the housing to provide waterproof protection for an inside of the electronic device.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: December 6, 2022
    Assignee: PEGATRON CORPORATION
    Inventors: Chien Yu Tsai, Shin Min Lee
  • Patent number: 11523434
    Abstract: A method for determining at least one random access channel (RACH) burst used by a user equipment (UE) including: determining a reference resource location by receiving a data service; and determining the resource location of the at least one random access channel burst according to the reference resource location and an offset.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: December 6, 2022
    Assignee: Acer Incorporated
    Inventors: Wei-Chen Pao, Chien-Min Lee
  • Publication number: 20220367337
    Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yuan Chen, Cheng-Hung Lee, Hung-Jen Liao, Hau-Tai Shieh, Kao-Cheng Lin, Wei-Min Chan
  • Patent number: 11498830
    Abstract: The invention provides a MEMS microphone. The MEMS microphone includes a substrate, having a first opening. A dielectric layer is disposed on the substrate, wherein the dielectric layer has a second opening aligned to the first opening. A diaphragm is disposed within the second opening of the dielectric layer, wherein a peripheral region of the diaphragm is embedded into the dielectric layer at sidewall of the second opening. A backplate layer is disposed on the dielectric layer and covering over the second opening. The backplate layer includes a plurality of acoustic holes arranged into a regular array pattern. The regular array pattern comprises a pattern unit, the pattern unit comprises one of the acoustic holes as a center hole, and peripheral holes of the acoustic holes surrounding the center hole with a same pitch to the center hole.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: November 15, 2022
    Assignee: Solid State System Co., Ltd.
    Inventors: Cheng-Wei Tsai, Tsung-Min Hsieh, Chien-Hsing Lee
  • Publication number: 20220302374
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, a top electrode layer on the magnetic tunnel junction stack, and a hard mask layer on said top electrode layer, wherein the material of top electrode layer is titanium nitride, a material of said hard mask layer is tantalum or tantalum nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Application
    Filed: June 9, 2022
    Publication date: September 22, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, JUN XIE
  • Patent number: 11450605
    Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Yuan Chen, Cheng-Hung Lee, Hung-Jen Liao, Hau-Tai Shieh, Kao-Cheng Lin, Wei-Min Chan
  • Patent number: 11452091
    Abstract: A communication device for handling a hybrid automatic repeat request (HARQ) transmission comprises a storage unit for storing instructions and a processing circuit coupled to the storage unit. The processing circuit is configured to execute the instructions stored in the storage unit. The instructions comprise performing a first downlink (DL) reception in a first subframe from a serving cell; and transmitting a first HARQ feedback in response to the first DL reception in a second subframe to the serving cell, wherein the second subframe is determined according to the first subframe and a sum of a predetermined timing and a first HARQ timing.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: September 20, 2022
    Assignee: ACER INCORPORATED
    Inventor: Chien-Min Lee
  • Publication number: 20220295555
    Abstract: A device for handling channel access procedure includes a storage device and a processing circuit coupled to the storage device and configured to execute instructions stored in the storage device. The storage device is configured for storing the instructions of receiving an indication for an uplink transmission; determining at least one parameter of the device for a listen-before-talk procedure according to a capability of the device or a signaling from a base station; and performing the uplink transmission according to the indication.
    Type: Application
    Filed: May 30, 2022
    Publication date: September 15, 2022
    Inventors: Li-Chung LO, Chien-Min LEE