Abstract: A magnetic memory device includes a spin-orbit torque (SOT) induction spin Hall electrode and a free layer of a magnetic tunnel junction (MTJ) stack disposed on the spin Hall electrode which is a synthetic anti-ferromagnetic structure. The free layer has a magnetic moment which is askew of the long axis of the MTJ stack and askew the direction of current flow through the spin Hall electrode. The MTJ stack internally generates a magnetic field to switch the state of the free layer. The free layer includes a first layer separated from a second layer by a spacer layer, where the first layer and the second layer may have the same or different crystalline structures.

Abstract: The disclosure is directed to a method used by a user equipment (UE) to communicate to a base station through a M-TRP in an unlicensed band and a UE using the same method. In one of the exemplary embodiments, the disclosure is directed to a method used by a UE to communicate to a base station through a M-TRP in an unlicensed band. The method would include not limited to: receiving, for a communication operation with a network, a configuration comprising multiple CORESETPoolIndexes; and receiving a PDCCH according to the configuration.

Abstract: A magnetic memory device includes a substrate, a spin-orbit torque (SOT) induction structure, and a magnetic tunnel junction (MTJ) stack. The SOT induction structure is disposed over the substrate. The SOT induction structure includes a metal and at least one dopant. The MTJ stack is disposed over the SOT induction structure.

Abstract: First fire operations for an ovonic threshold switch (OTS) selector is provided. A first fire operation includes setting a peak amplitude of a voltage pulse, and performing at least one cycle, including: providing the voltage pulse to the OTS selector; sensing an output current passing through the OTS selector in response to the received voltage pulse; comparing a peak amplitude of the voltage pulse with a maximum peak amplitude ensuring initialization of the OTS selector; ending the first fire operation if the peak amplitude reaches the maximum peak amplitude; comparing the output current with a target current indicative of initialization of the OTS selector if the peak amplitude is lower than the maximum peak amplitude; ending the first fire operation if the output current reaches the target current; and setting another voltage pulse with a greater peak amplitude if the output current is lower than the target current.

Abstract: A memory device includes a substrate, a spin-orbit torque (SOT) layer, a magnetic tunneling junction (MTJ) film stack, a connecting via and a shielding structure. The SOT layer is disposed on the substrate. The MTJ film stack is formed over SOT layer and on the substrate. The connecting via is disposed on and electrically connected to the MTJ film stack. The shielding structure is laterally surrounding the MTJ film stack and disposed on the SOT layer, wherein the shielding structure includes a first dielectric layer, a high magnetic permeability layer and a second dielectric layer, the first dielectric layer is in contact with the SOT layer and the MTJ film stack, and the high magnetic permeability layer is sandwiched between the first dielectric layer and the second dielectric layer.

Abstract: A magnetic memory device includes a spin-orbit torque (SOT) induction spin Hall electrode and a free layer of a magnetic tunnel junction (MTJ) stack disposed on the spin Hall electrode which is a synthetic anti-ferromagnetic structure. The free layer has a magnetic moment which is askew of the long axis of the MTJ stack and askew the direction of current flow through the spin Hall electrode. The MTJ stack internally generates a magnetic field to switch the state of the free layer. The free layer includes a first layer separated from a second layer by a spacer layer, where the first layer and the second layer may have the same or different crystalline structures.

Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.

Abstract: A memory device and a method of manufacturing the same are provided. The memory device includes a semiconductor substrate, an interconnect structure and a memory cell. The interconnect structure is disposed over the semiconductor substrate, and the memory cell is disposed over the interconnect structure and electrically coupled with the semiconductor substrate and the interconnect structure. The memory cell includes a spin Hall electrode layer, an MTJ pillar, a hard mask, and a spacer. The MTJ pillar is disposed on the spin Hall electrode layer, the hard mask is disposed on the MTJ pillar, and the spacer is disposed on sidewalls of the MTJ pillar and the hard mask. Suitably, the spin Hall electrode layer at least comprises an inner portion and an outer portion surrounding the inner portion, and a top surface of the outer portion is lower than a top surface of the inner portion.

Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.

Abstract: A magnetic memory device includes a spin-orbit torque (SOT) induction structure which may be strained and seedless and formed with a perpendicular magnetic anisotropy. A magnetic tunnel junction (MTJ) stack is disposed over the SOT induction structure. A spacer layer may decouple layers between the SOT induction structure and the MTJ stack or decouple layers within the MTJ stack. One end of the SOT induction structure may be coupled to a first transistor and another end of the SOT induction structure coupled to a second transistor.

Abstract: A memory device is provided. The memory device includes a substrate, a spin-orbit torque layer and a magnetic tunneling junction (MTJ). The MTJ stacks with the spin-orbit torque layer over the substrate and includes a synthetic free layer, a barrier layer and a reference layer. The synthetic free layer includes a synthetic antiferromagnetic structure, a first spacer layer and a free layer, wherein the synthetic antiferromagnetic structure is disposed between the spin-orbit torque layer and the free layer. The barrier layer is disposed beside the synthetic free layer. The reference layer is disposed beside the barrier layer.

Abstract: A method and a user equipment for reception of physical downlink shared channel and transmission of physical uplink control channel are provided. The method includes: receiving a first downlink control information; in response to a first field being included in the first downlink control information, obtaining a codepoint from the first field, wherein the codepoint is associated with a selection of at least one transmission configuration indicator state; and receiving the physical downlink shared channel according to the first downlink control information.

Abstract: An aspect of the disclosure includes a method for, including: receiving at least one indication indicating at least one of a DL reception and a UL transmission; and performing the DL reception through a first resource or the UL transmission through a second resource according to a rule.

Abstract: A transmission direction setting method, a user equipment (UE), and a network device are provided. In the method adapted for a UE, receiving a first configuration to indicate a first transmission direction for a frequency range within a time unit; receiving a second configuration to indicate a second transmission direction for a frequency segmentation within the time unit; and determining a third transmission direction for the frequency segmentation according to the second transmission direction. The frequency segmentation consists of one resource block (RB) or a set of consecutive RBs and is a part of the frequency range.

Abstract: A magnetic memory device includes a spin-orbit torque (SOT) induction structure which may be strained and seedless and formed with a perpendicular magnetic anisotropy. A magnetic tunnel junction (MTJ) stack is disposed over the SOT induction structure. A spacer layer may decouple layers between the SOT induction structure and the MTJ stack or decouple layers within the MTJ stack. One end of the SOT induction structure may be coupled to a first transistor and another end of the SOT induction structure coupled to a second transistor.

Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.

Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.

Abstract: According to an exemplary embodiment, the disclosure is directed to a method used by a UE to multiplex uplink transmissions. The method includes determining whether to multiplex a first plurality of UL channels in a first slot, where the UL channels overlap within at least one time period and are indicated with a first priority index; determining whether to multiplex a second plurality of UL channels in the first slot, where the second plurality of channels overlap within at least one time period and are indicated with a second priority index; determining whether to multiplex a third plurality of UL channels in the first slot, where the UL channels are indicated with different priority indexes; determining whether to prioritize a fourth plurality of UL channels in the first slot, wherein the UL channels are indicated with a different priority indexes; and performing an uplink transmission in the first slot.

Abstract: A communication device for handling a multi-cell scheduling includes at least one storage device; and at least one processing circuit, coupled to the at least one storage device, wherein the at least one storage device stores instructions, and the at least one processing circuit is configured to execute the instructions of: receiving a downlink (DL) control information (DCI) from a network; determining a plurality of first cells for at least one communication operation from a cell set according to the DCI; and performing the at least one communication operation with the network via at least one cell of the plurality of first cells.

Abstract: A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.