Abstract: A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a shared selector layer coupled to the first terminal.

Abstract: A method of handling communication for a communication device of a wireless communication system, wherein the communication device is configured with a plurality of frequency bands, includes the step of: receiving a downlink (DL) control signal from a network of the wireless communication system via a first frequency band among the plurality of frequency bands, wherein the DL control signal indicates whether at least one of the plurality of frequency bands is available or not available.

Abstract: A communication device for handling a hybrid automatic repeat request (HARQ) retransmission, is configured to execute the instructions of receiving a first physical downlink (DL) shared channel (PDSCH) from a network, wherein a first HARQ feedback corresponding to the first PDSCH is allocated in a first uplink (UL) channel and the first UL channel is corresponding to a first priority index; determining not to transmit the first HARQ feedback in the first UL channel; determining a second UL channel for the first HARQ feedback, wherein the second UL channel is corresponding to a second priority index; and transmitting the first HARQ feedback in the second UL channel.

Abstract: A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a shared selector layer coupled to the first terminal.

Abstract: A communication device for handling a reception comprises at least one storage device and at least one processing circuit, coupled to the at least one storage device. The at least one storage device stores instructions, and the at least one processing circuit is configured to execute the instructions of: receiving a DCI from a control resource set; and receiving a PDSCH according to the DCI, wherein the DCI comprising a TCI field, and the TCI field indicating a TCI codepoint corresponding to a first TCI state and a second TCI state.

Abstract: According to an exemplary embodiment, the disclosure is directed to a method used by a UE to multiplex uplink transmissions. The method includes determining whether to multiplex a first plurality of UL channels in a first slot, where the UL channels overlap within at least one time period and are indicated with a first priority index; determining whether to multiplex a second plurality of UL channels in the first slot, where the second plurality of channels overlap within at least one time period and are indicated with a second priority index; determining whether to multiplex a third plurality of UL channels in the first slot, where the UL channels are indicated with different priority indexes; determining whether to prioritize a fourth plurality of UL channels in the first slot, wherein the UL channels are indicated with a different priority indexes; and performing an uplink transmission in the first slot.

Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.

Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.

Abstract: The disclosure is directed to a method used by a user equipment (UE) to communicate to a base station through a M-TRP in an unlicensed band and a UE using the same method. In one of the exemplary embodiments, the disclosure is directed to a method used by a UE to communicate to a base station through a M-TRP in an unlicensed band. The method would include not limited to: receiving, for a communication operation with a network, a configuration comprising multiple CORESETPoolIndexes; and receiving a PDCCH according to the configuration.

Abstract: A UE for beam failure detection is provided. The RF signal processing device of the UE assesses a first radio link quality according to a first BFD-reference signal (BFD-RS) set including at least one reference signal, communicating with a plurality of transmission/reception points (TRPs) which include at least a first TRP and a second TRP. The processor of the UE is coupled to the RF signal processing device. When the first radio link quality is below a threshold, the processor generates a first indication, wherein the first indication is a first beam failure instance (BFI) or the first BFD-RS set. The processor enables a first timer and a first counter according to the first indication.

Abstract: A UE for beam failure detection is provided. The UE includes a radio frequency (RF) signal processing device. The RF signal processing device receives a first candidate-beam reference-signal (RS) list and a second candidate-beam RS list and reports a beam failure information. The first candidate-beam RS list is associated with a first beam-failure-detection RS (BFD-RS) set and the second candidate-beam RS list is associated with a second BFD-RS set. The beam failure information includes at least one of following: at least on component carrier (CC) index, at least one new candidate beam, an identity of BFD-RS set, or an CORESETPoolIndex.

Abstract: A communication device for handling transmission/reception for a serving cell comprises a storage unit for storing instructions and a processing circuit coupled to the storage unit. The processing circuit is configured to execute the instructions stored in the storage unit. The instructions comprise receiving an indication indicating at least one subband unit of a serving cell from a network; and performing a communication operation in the at least one subband unit with the network, after receiving the indication.

Abstract: A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.

Abstract: A communication device for handling a plurality of physical downlink (DL) shared channels (PDSCHs) in a plurality of bandwidth parts (BWPs) comprises at least one storage device; and at least one processing circuit, coupled to the at least one storage device. The at least one storage device stores instructions, and the at least one processing circuit is configured to execute the instructions of: receiving a first PDSCH in a first BWP in a time period from a network; receiving a second PDSCH in a second BWP in the time period from the network, wherein the first PDSCH is corresponding to a first processing priority and the second PDSCH is corresponding to a second processing priority; and processing the second PDSCH according to the second processing priority.

Abstract: A communication device for handling a bandwidth part (BWP) switching comprises at least one storage device; and at least one processing circuit, coupled to the at least one storage device. The at least one storage device stores instructions, and the at least one processing circuit is configured to execute the instructions of performing the BWP switching from a first BWP to a second BWP; generating a BWP adaptation indication according to a BWP configuration; and transmitting the BWP adaptation indication.

Abstract: An aspect of the disclosure includes a method for, including: determining a first set of candidate number of a first set of aggregation level (AL) for receiving a first DCI; and receiving the first DCI according to the first set of candidate number and the first set of AL on a first cell, wherein the first DCI is configured for scheduling PDSCHs on a plurality of cells, and the plurality of cells comprises a second cell and a third cell, and the first set of candidate number and the first set of AL are corresponding to a search space with a first identity.

Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.

Abstract: A magnetic memory device includes a spin-orbit torque (SOT) induction spin Hall electrode and a free layer of a magnetic tunnel junction (MTJ) stack disposed on the spin Hall electrode which is a synthetic anti-ferromagnetic structure. The free layer has a magnetic moment which is askew of the long axis of the MTJ stack and askew the direction of current flow through the spin Hall electrode. The MTJ stack internally generates a magnetic field to switch the state of the free layer. The free layer includes a first layer separated from a second layer by a spacer layer, where the first layer and the second layer may have the same or different crystalline structures.

Abstract: A magnetic memory device includes a spin-orbit torque (SOT) induction structure which may be strained and seedless and formed with a perpendicular magnetic anisotropy. A magnetic tunnel junction (MTJ) stack is disposed over the SOT induction structure. A spacer layer may decouple layers between the SOT induction structure and the MTJ stack or decouple layers within the MTJ stack. One end of the SOT induction structure may be coupled to a first transistor and another end of the SOT induction structure coupled to a second transistor.

Abstract: Some embodiments relate to a method for manufacturing a memory device. The method includes forming a bottom electrode layer over a substrate. A first etch process is performed, thereby defining one or more holes in the bottom electrode layer and defining a bottom electrode. A pair of insulators are formed within the one or more holes such that the insulators are disposed on opposing sides of the bottom electrode. A buffer layer, a seed layer, a magnetic tunnel junction (MTJ) stack, and a top electrode are formed over the bottom electrode. A second etch process is performed to remove a portion of the buffer layer, the seed layer, the MTJ stack, and the top electrode, thereby defining a memory cell.