Patents by Inventor Chien-Ping Huang
Chien-Ping Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9425152Abstract: An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first surface, metallic pillars formed on the first surface, a chip mounted on and electrically connected to the die-mounting area, an encapsulant covering the chip and the first surface while exposing a portion of each of the metallic pillars from the encapsulant, and a shielding film enclosing the encapsulant and electrically connecting to the metallic pillars. A fabrication method of the above structure by two cutting processes is further provided. The first cutting process forms grooves by cutting the encapsulant. After a shielding film is formed in the grooves and electrically connected to the metallic pillars, the complete package structure is formed by the second cutting process, thereby simplifying the fabrication process while overcoming inferior grounding of the shielding film as encountered in prior techniques.Type: GrantFiled: February 13, 2015Date of Patent: August 23, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chin-Tsai Yao, Chien-Ping Huang, Chun-Chi Ke
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Publication number: 20160233115Abstract: A cleaning apparatus for a semiconductor equipment is provided. The cleaning apparatus comprising a cleaning pad with a plurality of brushes thereon is located on a rotor of the semiconductor equipment to remove residues within the semiconductor equipment by using the brushes against the residues via moving and rotating the rotor and the cleaning apparatus.Type: ApplicationFiled: April 20, 2016Publication date: August 11, 2016Inventors: Chien-Ping HUANG, Tsan-Hua Huang, Tsung-Hsun HAN, Kian-Poh WONG
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Patent number: 9390959Abstract: A semiconductor package is provided, including a substrate having a top surface, a bottom surface opposing the top surface, a via communicating the top surface with the bottom surface, and a stator set formed by circuits; an axial tube axially installed in the via of the substrate; a plurality of electronic components mounted on the top surface of the substrate and electrically connected to the substrate; an encapsulant formed on the top surface of the substrate for encapsulating the electronic components and the axial tube; and an impeller axially coupled to the axial tube via the bottom surface of the substrate. In the semiconductor package, the stator set is formed in the substrate by a patterning process. Therefore, the thickness of the semiconductor package is reduced significantly.Type: GrantFiled: April 11, 2013Date of Patent: July 12, 2016Assignee: Amtek Semiconductors Co., Ltd.Inventor: Chien-Ping Huang
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Patent number: 9252074Abstract: A heat dissipating device includes a semiconductor packaging structure having a stator set and a semiconductor element provided therein, a fan wheel set pivotally connected to the semiconductor packaging structure, and a guiding structure having a guiding channel. The guiding structure receives the semiconductor packaging structure and the fan wheel set. The fan wheel set includes a plurality of blades located above the surface of the semiconductor packaging structure. The stator set and the semiconductor element controls the first blades. The blades extend beyond side surfaces the semiconductor packaging structure and have their sizes increased, such that the airflow volume can be increased without changing the size of the semiconductor packaging structure.Type: GrantFiled: October 30, 2013Date of Patent: February 2, 2016Assignee: Amtek Semiconductors Co., Ltd.Inventor: Chien-Ping Huang
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Patent number: 9190387Abstract: A quad flat non-leaded (QFN) package structure with an electromagnetic interference (EMI) shielding function is proposed, including: a lead frame having a die pad, a plurality of supporting portions connecting to the die pad and a plurality of leads disposed around the periphery of the die pad without connecting to the die pad; a chip mounted on the die pad; bonding wires electrically connecting the chip and the leads; an encapsulant for encapsulating the chip, the bonding wires and the lead frame and exposing the side and bottom surfaces of the leads and the bottom surface of the die pad; and a shielding film disposed on the top and side surfaces of the encapsulant and electrically connecting to the supporting portions for shielding from EMI. A method of fabricating the package structure as described above is further proposed.Type: GrantFiled: April 15, 2014Date of Patent: November 17, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chin-Tsai Yao, Chien-Ping Huang, Chun-Chi Ke
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Patent number: 9190296Abstract: A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.Type: GrantFiled: June 30, 2014Date of Patent: November 17, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
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Patent number: 9177837Abstract: A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.Type: GrantFiled: March 21, 2014Date of Patent: November 3, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Pang-Chun Lin, Chun-Yuan Li, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
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Patent number: 9126214Abstract: A showerhead is disclosed in this invention. The showerhead includes a bottom portion, at least one plate, and a top portion. The bottom portion includes a plurality of gas tubes which are integratedly formed on the bottom portion. The gas tubes include at least one first gas tube. The at least one plate includes a first plate. The first plate includes a plurality of first openings, wherein the gas tubes pass through the first openings. The top portion is coupled to the bottom portion for forming at least one inner space.Type: GrantFiled: June 18, 2013Date of Patent: September 8, 2015Assignee: Hermes-Epitek CorporationInventors: Chien-Ping Huang, Tsan-Hua Huang
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Publication number: 20150155240Abstract: An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first surface, metallic pillars formed on the first surface, a chip mounted on and electrically connected to the die-mounting area, an encapsulant covering the chip and the first surface while exposing a portion of each of the metallic pillars from the encapsulant, and a shielding film enclosing the encapsulant and electrically connecting to the metallic pillars. A fabrication method of the above structure by two cutting processes is further provided. The first cutting process forms grooves by cutting the encapsulant. After a shielding film is formed in the grooves and electrically connected to the metallic pillars, the complete package structure is formed by the second cutting process, thereby simplifying the fabrication process while overcoming inferior grounding of the shielding film as encountered in prior techniques.Type: ApplicationFiled: February 13, 2015Publication date: June 4, 2015Inventors: Chin-Tsai Yao, Chien-Ping Huang, Chun-Chi Ke
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Chip scale package with electronic component received in encapsulant, and fabrication method thereof
Patent number: 9040361Abstract: A CSP includes: a hard board having a first wiring layer with conductive pads; a plurality of conductive elements disposed on at least a portion of the conductive pads; an electronic component having opposite active and inactive surfaces and being mounted on the hard board via the inactive surface; an encapsulating layer disposed on the hard board for encapsulating the conductive elements and electronic component, the active surface of the electronic component and the surfaces of the conductive elements being exposed through the encapsulating layer; a first dielectric layer and a third wiring layer disposed on the encapsulating layer, the third wiring layer being electrically connected to the conductive elements and the electronic component and further electrically connected to the first wiring layer through the conductive elements, thereby obtaining a stacked connection structure without the need of PTHs and using the hard board as a main structure to avoid warpage.Type: GrantFiled: December 2, 2010Date of Patent: May 26, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chiang-Cheng Chang, Chien-Ping Huang, Chun-Chi Ke, Hsin-Yi Liao, Hsi-Chang Hsu -
Patent number: 8981575Abstract: A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques.Type: GrantFiled: March 15, 2013Date of Patent: March 17, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Pang-Chun Lin, Chun-Yuan Li, Chien-Ping Huang, Chun-Chi Ke
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Patent number: 8975734Abstract: A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.Type: GrantFiled: December 14, 2010Date of Patent: March 10, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
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Patent number: 8963298Abstract: An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first surface, metallic pillars formed on the first surface, a chip mounted on and electrically connected to the die-mounting area, an encapsulant covering the chip and the first surface while exposing a portion of each of the metallic pillars from the encapsulant, and a shielding film enclosing the encapsulant and electrically connecting to the metallic pillars. A fabrication method of the above structure by two cutting processes is further provided. The first cutting process forms grooves by cutting the encapsulant. After a shielding film is formed in the grooves and electrically connected to the metallic pillars, the complete package structure is formed by the second cutting process, thereby simplifying the fabrication process while overcoming inferior grounding of the shielding film as encountered in prior techniques.Type: GrantFiled: April 28, 2010Date of Patent: February 24, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chin-Tsai Yao, Chien-Ping Huang, Chun-Chi Ke
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Patent number: 8901864Abstract: Proposed is a driver having dead-time compensation function. The driver having dead-time compensation function generates an output voltage according to a voltage command and a frequency command. The driver includes an inverter, an output current detector and a control unit. The inverter receives a DC voltage and operates with a pulse width modulation mode so that the driver outputs the output voltage and an output current. The output current detector detects the current value of the output current to generate a output current detecting signal. The control unit outputs a switching control signal to inverter according to the voltage command and the frequency command. The control unit corrects a reference command according to dead-time and the output current detecting signal related to the output current so that amplitude and waveform smoothness of the output voltage and the output current are compensated.Type: GrantFiled: August 20, 2012Date of Patent: December 2, 2014Assignee: Delta Electronics, Inc.Inventors: Chien-Yu Chi, Chien-Ping Huang
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Patent number: 8873244Abstract: A package structure includes a base body having a first encapsulant and a wiring layer embedded in and exposed from the first encapsulant. The wiring layer has a plurality of conductive traces and a plurality of first electrical contact pads. The first encapsulant has openings for exposing the first electrical contact pads, a chip electrically connected to the wiring layer, and a second encapsulant formed on the base body for covering the chip and the wiring layer, thereby providing an even surface for preventing the encapsulant from cracking when the chip is mounted.Type: GrantFiled: April 13, 2010Date of Patent: October 28, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Pang-Chun Lin, Hsiao-Jen Hung, Chun-Yuan Li, Chien-Ping Huang, Chun-Chi Ke
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Publication number: 20140315351Abstract: A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.Type: ApplicationFiled: June 30, 2014Publication date: October 23, 2014Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
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Publication number: 20140227830Abstract: A quad flat non-leaded (QFN) package structure with an electromagnetic interference (EMI) shielding function is proposed, including: a lead frame having a die pad, a plurality of supporting portions connecting to the die pad and a plurality of leads disposed around the periphery of the die pad without connecting to the die pad; a chip mounted on the die pad; bonding wires electrically connecting the chip and the leads; an encapsulant for encapsulating the chip, the bonding wires and the lead frame and exposing the side and bottom surfaces of the leads and the bottom surface of the die pad; and a shielding film disposed on the top and side surfaces of the encapsulant and electrically connecting to the supporting portions for shielding from EMI. A method of fabricating the package structure as described above is further proposed.Type: ApplicationFiled: April 15, 2014Publication date: August 14, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chin-Tsai Yao, Chien-Ping Huang, Chun-Chi Ke
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Patent number: 8802507Abstract: A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.Type: GrantFiled: November 2, 2012Date of Patent: August 12, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Cheng-Chia Chiang, Chin-Huang Chang, Chien-Ping Huang, Chih-Ming Huang, Jung-Pin Huang
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Publication number: 20140206146Abstract: A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.Type: ApplicationFiled: March 21, 2014Publication date: July 24, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Pang-Chun Lin, Chun-Yuan Li, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
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Publication number: 20140203450Abstract: A semiconductor package is provided, including a substrate having a top surface, a bottom surface opposing the top surface, a via communicating the top surface with the bottom surface, and a stator set formed by circuits; an axial tube axially installed in the via of the substrate; a plurality of electronic components mounted on the top surface of the substrate and electrically connected to the substrate; an encapsulant formed on the top surface of the substrate for encapsulating the electronic components and the axial tube; and an impeller axially coupled to the axial tube via the bottom surface of the substrate. In the semiconductor package, the stator set is formed in the substrate by a patterning process. Therefore, the thickness of the semiconductor package is reduced significantly.Type: ApplicationFiled: April 11, 2013Publication date: July 24, 2014Applicant: Amtek Semiconductors Co., Ltd.Inventor: Chien-Ping Huang