Abstract: A semiconductor device and a fabrication method thereof are provided. An opening having at least one slanted side is formed on a substrate. At least one chip and at least one passive component are mounted on the substrate. An encapsulant having a cutaway corner is formed on the substrate to encapsulate the chip and the passive component, wherein the cutaway corner of the encapsulant is spaced apart from the slanted side of the opening by a predetermined distance. A singulation process is performed to cut the encapsulant to form a package with a chamfer. The package is embedded in a lid to form the semiconductor device, wherein a portion of the substrate located between the slanted side of the opening and the cutaway corner of the encapsulant is exposed from the encapsulant to form an exposed portion. The present invention also provides a carrier for the semiconductor device.

Abstract: The present invention provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a chip having an active surface and an opposing non-active surface, wherein a plurality of bond pads are formed on the active surface, and first metal layers are formed on the bond pads and to edges of the non-active surface; conductive traces disposed on the non-active surface of the chip; a dielectric layer covering sides of the chip and formed with a plurality of openings therein to expose a portion of the conductive traces; and a plurality of second metal layers formed in the openings of the dielectric layer and on the first metal layers, such that the bond pads are electrically connected to the conductive traces via the first and second metal layers.

Abstract: A heat-dissipating semiconductor package structure and a method for manufacturing the same is disclosed. The method includes: disposing on and electrically connecting to a chip carrier at least a semiconductor chip and a package unit; disposing on the top surface of the package unit a heat-dissipating element having a flat portion and a supporting portion via the flat portion; receiving the package unit and semiconductor chip in a receiving space formed by the flat portion and supporting portion of the heat-dissipating element; and forming on the chip carrier encapsulant for encapsulating the package unit, semiconductor chip, and heat-dissipating element. The heat-dissipating element dissipates heat generated by the package unit, provides EMI shielding, prevents delamination between the package unit and the encapsulant, decreases thermal resistance, and prevents cracking.

Abstract: A stackable semiconductor device and a manufacturing method thereof are disclosed. The method includes providing a wafer comprised of a plurality of chips, wherein a plurality of solder pads are formed on the active surface of each chip, and a plurality of grooves are formed between the solder pads of any two adjacent ones of the chips; forming a dielectric layer on regions between the solder pads of any two adjacent ones of the chips ; forming a metal layer on the dielectric layer electrically connected to the solder pads and forming a connective layer on the metal layer, wherein the width of the connective layer is smaller than that of the metal layer; cutting along the grooves to break off the electrical connection between adjacent chips; thinning the non-active surface of the wafer to the extent that the metal layer is exposed from the wafer; and separating the chips to form a plurality of stackable semiconductor devices.

Abstract: A method for fabricating semiconductor packages is disclosed, including mounting and electrically connecting a semiconductor chip onto a chip carrier; mounting a heat-dissipating structure on the semiconductor chip; placing the heat-dissipating structure into a mold cavity for filling therein a packaging material to form an encapsulant, wherein the heat-dissipating structure has a heat spreader having a size larger than that of the predetermined size of the semiconductor package, a covering layer formed on the, and a plurality of protrusions formed on edges of the covering layer that are free from being corresponding in position to the semiconductor chip, such that the protrusions can abut against a top surface of the mold cavity to prevent the heat spreader from being warped; and finally performing a singulation process according to the predetermined size and removing the encapsulant formed on the covering layer to form the desired semiconductor package.

Abstract: A heat dissipation unit and a semiconductor package having the same are disclosed. The semiconductor package includes a carrier; an electronic component mounted on and electrically connected to the carrier; a heat dissipation unit, which includes a flat section attached to the electronic component, extension sections connected to the flat section, and a heat dissipation section connected to the extension sections; and an encapsulant encapsulating the electronic component and the heat dissipation unit, wherein stress releasing sections are at least disposed at intersectional corners between the extension sections and the flat section so as to prevent projections from being formed by concentrated stresses in a punching process of the heat dissipation unit, thereby maintaining flatness of the flat section and further preventing circuits of the electronic component from being damaged due to a contact point produced between the electronic component and the flat section in a molding process.

Abstract: A sensor-type semiconductor device and manufacturing method thereof are disclosed.

Abstract: The invention provides a stackable semiconductor device and a fabrication method thereof, including providing a wafer having a plurality of dies mounted thereon, both the die and the wafer having an active surface and a non-active surface opposing one another respectively, wherein each die has a plurality of solder pads formed on the active surface thereof and a groove formed between adjacent solder pads to form a first metal layer therein that is electrically connected to the solder pads; subsequently thinning the non-active surface of the wafer to where the grooves are located to expose the first metal layer therefrom, and forming a second metal layer on the non-active surface of the wafer for electrically connecting with the first metal layer; and separating the dies to form a plurality of stackable semiconductor devices.

Abstract: A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires.

Abstract: A leadframe-based semiconductor package and a fabrication method thereof are provided. The leadframe-based semiconductor package includes a chip implanted with a plurality of first and second conductive bumps thereon, and a leadframe having a plurality of leads. The first conductive bumps are bonded to the leads to electrically connect the chip to the leadframe. The chip, the first and second conductive bumps, and the leadframe are encapsulated by an encapsulant, with bottom ends of the second conductive bumps and bottom surfaces of the leads being exposed from the encapsulant. This allows the second conductive bumps to provide additional input/output electrical connections for the chip besides the leads.

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

Abstract: This invention provides a method for fabricating a semiconductor device and a carrier applied therein. The method includes the steps of: disposing a chip-mounted substrate in an opening of a carrier; forming at least a storage aperture and at least an inspection aperture in the carrier; infusing an adhesive into the storage aperture to fill a gap between the substrate and carrier with the adhesive by capillarity; determining whether the inspection aperture is filled with the adhesive to ascertain whether the gap is completely filled with the adhesive; in response to a positive result, performing a molding process to form a molding compound for encapsulating the chip; and performing implantation of solder ball and a singulation process to form a semiconductor device with desirable dimensions.

Abstract: A semiconductor device having conductive bumps and a fabrication method thereof is proposed. The fabrication method includes the steps of forming a first metallic layer on a substrate having solder pads and a passivation layer formed thereon, and electrically connecting it to the solder pads; applying a second covering layer over exposed parts of the first metallic layer; subsequently, forming a second metallic layer on the second covering layer, and electrically connecting it to the exposed parts of the first metallic layer; applying a third covering layer, and forming openings for exposing parts of the second metallic layer to form thereon a conductive bump having a metallic standoff and a solder material. The covering layers and the metallic layers can provide a buffering effect for effectively absorbing the thermal stress imposed on the conductive bumps to prevent delamination caused by the UBM layers.

Abstract: The present invention provides a sensor-type semiconductor package and a method for fabricating the same. The method includes the steps of: providing a wafer having a plurality of sensor chips for mounting the wafer on a carrier board having an insulation layer, a plurality of conductive traces, and a substrate; forming a plurality of grooves among the solder pads on the active surfaces of the adjacent sensor chips, so as to expose the conductive traces and form a metal layer in the grooves, to electrically connect to the solder pads on the active surfaces of the adjacent sensor chips and the conductive traces; disposing a transparent medium on the wafer to cover the sensing areas of the sensor chips; removing the substrate, so as to expose the conductive traces and the insulation layer; and cutting the sensor chips along the borders to form a plurality of sensor-type semiconductor packages.

Abstract: This invention discloses a sensor semiconductor device and a manufacturing method thereof, including: providing a wafer having a plurality of sensor chips, forming a plurality of grooves between bond pads on active surfaces of the adjacent sensor chips; forming conductive traces in the grooves for electrically connecting the bond pads; mounting a transparent medium on the wafer for covering sensing areas of the sensor chips; thinning the sensor chips from the non-active surfaces down to the grooves, thereby exposing the conductive traces; cutting the wafer to separate the sensor chips; mounting the sensor chips on a substrate module having a plurality of substrates, electrically connecting the conductive traces to the substrates; providing an insulation material on the substrate module and between the sensor chips so as to encapsulate the sensor chips but expose the transparent medium; and cutting the substrate module to separate a plurality of resultant sensor semiconductor devices.

Abstract: A photosensitive semiconductor package, a method for fabricating the same, and a lead frame thereof are proposed. The lead frame has a die pad and a plurality of leads, wherein at least one recessed portion is formed at an end of each lead close to the die pad, and at least one recessed region is formed on the die pad. An encapsulant fills the recessed portions, the recessed region, and between the leads and the die pad, and is formed on the lead frame to define a chip receiving cavity. A photosensitive chip is mounted in the chip receiving cavity, wherein at least partially a non-active surface of the chip is attached to the encapsulant filling the recessed region and is not in contact with the recessed region. A light-penetrable unit is attached to the encapsulant formed on the lead frame to seal the chip receiving cavity.

Abstract: A sensor semiconductor package and a fabrication method thereof are provided in the present application. The fabrication method comprises steps of: forming a plurality of grooves on a wafer between bond pads on active surfaces of every adjacent chips; forming metal layers in the grooves for electrically connecting with the bond pads of adjacent chips; thinning the non-active surfaces to expose the metal layers therefrom; forming a cover layer on the non-active surfaces with the metal layers are exposed therefrom; forming a solder resist layer on the covering layer and the conductive wirings with terminals of the conductive wirings are exposed therefrom; and cutting along cutting paths between every sensor chips to form a plurality of sensor semiconductor packages. Accordingly, the prior art problems such as misalignment of forming beveled grooves, concentrated stress and breakage can be solved.

Abstract: A semiconductor substrate having a body and a plurality of finger pads formed thereon is disclosed. Each of the finger pads includes two expanding portions respectively and a connecting portion formed therebetween. The finger pads are alternately arranged on the body in a manner that one of the expanding portions of one of the finger pads is disposed in position corresponding to the connecting portion of an adjacent one of the finger pads, so as to reduce pitches between the finger pads horizontally and vertically, provide sufficient spaces for wire bonding, and prevent a wire bonder from mistakenly recognizing a lead trace coupled to the finger pad as another finger pad.

Abstract: A semiconductor package substrate proposed by the invention includes a base body and a plurality of finger pads disposed on surface of the base body, wherein the finger pads are arranged in such a way that an angle is formed between connecting line of centers of two adjacent finger pads and the direction in which the finger pads are arranged. The finger pads are waterdrop shaped finger pads with arc ends and angle ends alternately disposed on surface of the substrate, alternately disposed waterdrop shaped finger pads and arc shaped finger pads, or alternately disposed arc shaped finger pads at a predetermined spacing. According to the present invention, distance between adjacent finger pads is reduced and problem of short circuit as a result of erroneous contact between bonding wire and adjacent finger pad is prevented.

Abstract: A semiconductor device and a fabrication method thereof are provided. A semiconductor substrate having a plurality of bonding pads is prepared, and a first passivation layer, a second passivation layer and a metallic layer are successively formed on the semiconductor substrate. A third passivation layer is further applied on the semiconductor substrate and has a plurality of openings for exposing a portion of the metallic layer, wherein each of the openings is shifted in position from a corresponding one of the bonding pads by a distance not exceeding a radius of the bonding pad. A plurality of solder bumps are bonded to the exposed portion of the metallic layer and have a larger contact area with the third passivation layer. This provides better buffer to reduce stress exerted on the solder bumps, thereby preventing problems of cracking and delamination as in the prior art.