Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.

Abstract: A motor driving device includes a first hysteresis comparator, a second hysteresis comparator, a logic circuit, a control unit, and an inverter circuit. The logic circuit receives a start signal or a start completion signal to output the first output signal as a commutation signal according to the start signal, or to output the second output signal as the commutation signal according to the start completion signal, clamps the second output signal by the first output signal, stops outputting the commutation signal after the potential state of the commutation signal is changed, and unclamps the second output signal with the first output signal and outputs the commutation signal in response to a difference voltage between the first input signal and the second input signal being greater than a positive value of the first hysteresis voltage or less than a negative value of the first hysteresis voltage.

Abstract: The present invention provides a capacitor structure including a metal oxide semiconductor (MOS) capacitor and a metal oxide metal (MOM) capacitor. A gate electrode, a source electrode and a drain electrode of the MOS capacitor have a first finger-shaped structure implemented by a first metal layer. The MOM capacitor comprises a second finger-shaped structure implemented by a second metal layer. The second metal layer is adjacent to the first metal layer in a vertical direction.

Abstract: A motor driving device includes a first hysteresis comparator, a second hysteresis comparator, a logic circuit, a control unit, and an inverter circuit. The logic circuit receives a start signal or a start completion signal to output the first output signal as a commutation signal according to the start signal, or to output the second output signal as the commutation signal according to the start completion signal, clamps the second output signal by the first output signal, stops outputting the commutation signal after the potential state of the commutation signal is changed, and unclamps the second output signal with the first output signal and outputs the commutation signal in response to a difference voltage between the first input signal and the second input signal being greater than a positive value of the first hysteresis voltage or less than a negative value of the first hysteresis voltage.

Abstract: A delay circuit includes an inverting receiving circuit, a reference point generating circuit, a first buffer gate and a first inverter. An inverting receiving circuit includes a first transistor and a first switching circuit. The reference point generating circuit includes a compensation resistor, a capacitor element, and a first current source. In response to the input signal being at a first potential, a voltage of the output node starts to decrease from a voltage reference point. In response to at least one of a manufacturing process, the first reference voltage, and a temperature being changed, the compensation resistor is configured to correct the voltage reference point.

Abstract: A delay circuit includes an inverting receiving circuit, a reference point generating circuit, a first buffer gate and a first inverter. An inverting receiving circuit includes a first transistor and a first switching circuit. The reference point generating circuit includes a compensation resistor, a capacitor element, and a first current source. In response to the input signal being at a first potential, a voltage of the output node starts to decrease from a voltage reference point. In response to at least one of a manufacturing process, the first reference voltage, and a temperature being changed, the compensation resistor is configured to correct the voltage reference point.

Abstract: A phase-locked loop circuit includes a delay phase-locked loop and a sub-sampling phase-locked loop. The delay phase-locked loop phase locks a first reference clock and a second reference clock to an input clock, and includes a phase correction circuit, an integrator, a first sub-sampling phase detector, and a first charge pump. The sub-sampling phase-locked loop is configured to generate an output clock with a predetermined phase-locked loop frequency, and the output clock is phase-locked to the first reference clock, the sub-sampling phase-locked loop includes a second sub-sampling phase detector, a second charge pump, a phase frequency detecting circuit, a voltage controlled oscillator and a first frequency divider. The first sub-sampling phase detector and the second sub-sampling phase detector have a symmetric circuit structure, and a first charge pump circuit and a second charge pump circuit have a symmetric circuit structure.

Abstract: A touch display device includes a printed circuit board and a cover. The printed circuit board has a top surface, a bottom surface and soldering points. The printed circuit board includes a first printed circuit, a light element and a second printed circuit. A part of the first printed circuit is on the top surface or the bottom surface and connected with the corresponding soldering point. The light emitting element is on the top surface and electrically connected to the first printed circuit. On the top surface, the second printed circuit does not overlap with the first printed circuit. The cover covers the printed circuit board. The cover has light transmission areas which are aligned with the light elements. The second printed circuit is configured to provide a capacitance value coupled to a capacitive sensing element coupled between the second printed circuit and the cover.

Abstract: A data merge method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: obtaining a first logical distance value between a first physical unit and a second physical unit among the physical units, and the first logical distance value reflects a logical dispersion degree between at least one first logical unit mapped by the first physical unit and at least one second logical unit mapped by the second physical unit; and performing a data merge operation according to the first logical distance value, so as to copy valid from a source node to a recycling node.

Abstract: A processing device for position sensing includes a plurality of light sensors, a signal processing unit, a current mirror unit and a transforming unit. The light sensors are spaced apart from each other and sense a light field to generate a plurality of position sensing current signals. The signal processing unit receives the position sensing current signals and provides a load isolation, so as to generate a first current signal and a second current signal. The second current signal is transmitted to a node. The first and second current signals respectively correspond to a first group and a second group of light sensors. The current mirror unit mirrors the first current signal to a third current signal. The third current is transmitted to the node. The transforming unit transforms a differential current signal formed by the second and third current signals on the node to a voltage signal.

Abstract: A back cover includes a metal body having a first side, a second side, and a groove that is formed at the first side. The metal body further has a first radiator, a second radiator, and a ground radiator. The first radiator is disposed in the groove, and has a main portion and a support portion that cooperatively form a T-shape. The main portion includes a feeding end adjacent to a closed end of the groove. The second radiator is adjacently connected to the groove and is defined by the first and second sides, and an edge of the groove. The ground radiator is formed by a portion of the metal body excluding the first and second radiators. The second radiator and the support portion are connected to the ground radiator. The first and second radiators, and the ground radiator are serve as an antenna structure.

Abstract: A processing device for position sensing includes a plurality of light sensors, a signal processing unit, a current mirror unit and a transforming unit. The light sensors are spaced apart from each other and sense a light field to generate a plurality of position sensing current signals. The signal processing unit receives the position sensing current signals and provides a load isolation, so as to generate a first current signal and a second current signal. The second current signal is transmitted to a node. The first and second current signals respectively correspond to a first group and a second group of light sensors. The current mirror unit mirrors the first current signal to a third current signal. The third current is transmitted to the node. The transforming unit transforms a differential current signal formed by the second and third current signals on the node to a voltage signal.

Abstract: Clock adjustment circuits and clock adjustment methods are provided. The clock adjustment circuit is configured to generate an output clock and includes a phase interpolator, a logic circuit, and an integrator. The phase interpolator is configured to generate by interpolation an intermediate clock according to a first reference clock, a second reference clock, and a control signal. The frequencies of the first reference clock, the second reference clock and the intermediate clock are substantially the same. The logic circuit is coupled to the phase interpolator and configured to generate the output clock according to the intermediate clock and one of the first reference clock and the second reference clock. The integrator is coupled to the phase interpolator and the logic circuit and configured to generate the control signal according to the output clock. The control signal varies with an average based on a duty cycle of the output clock.

Abstract: Clock adjustment circuits and clock adjustment methods are provided. The clock adjustment circuit is configured to generate an output clock and includes a phase interpolator, a logic circuit, and an integrator. The phase interpolator is configured to generate by interpolation an intermediate clock according to a first reference clock, a second reference clock, and a control signal. The frequencies of the first reference clock, the second reference clock and the intermediate clock are substantially the same. The logic circuit is coupled to the phase interpolator and configured to generate the output clock according to the intermediate clock and one of the first reference clock and the second reference clock. The integrator is coupled to the phase interpolator and the logic circuit and configured to generate the control signal according to the output clock. The control signal varies with an average based on a duty cycle of the output clock.

Abstract: The present invention discloses a circuit capable of protecting low-voltage devices. The circuit includes: a pin configured to receive a signal of an external device; a control voltage generating circuit configured to generate a first control voltage according to a supply voltage to turn on a protected device when the supply voltage is at a high level, and generate a second control voltage according to a voltage of the pin to turn on the protected device when the supply voltage is at a low level; and the protected device configured to be turned on according to one of the first and the second control voltages and thereby electrically couple the pin with an internal circuit, in which the difference between the voltage of the pin and each of the first and the second control voltages is within a maximum withstanding voltage of the protected device.

Abstract: A data merge method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: obtaining a first logical distance value between a first physical unit and a second physical unit among the physical units, and the first logical distance value reflects a logical dispersion degree between at least one first logical unit mapped by the first physical unit and at least one second logical unit mapped by the second physical unit; and performing a data merge operation according to the first logical distance value, so as to copy valid from a source node to a recycling node.

Abstract: A back cover includes a metal body having a first side, a second side, and a groove that is formed at the first side. The metal body further has a first radiator, a second radiator, and a ground radiator. The first radiator is disposed in the groove, and has a main portion and a support portion that cooperatively form a T-shape. The main portion includes a feeding end adjacent to a closed end of the groove. The second radiator is adjacently connected to the groove and is defined by the first and second sides, and an edge of the groove. The ground radiator is formed by a portion of the metal body excluding the first and second radiators. The second radiator and the support portion are connected to the ground radiator. The first and second radiators, and the ground radiator are serve as an antenna structure.

Abstract: Clock adjustment circuits and clock adjustment methods are provided. The clock adjustment circuit is configured to adjust an input clock to generate an output clock and includes a low-pass filter, a direct current (DC) control circuit, a DC offset amplifier, an amplifier, and an integrator. The low-pass filter filters the input clock to generate a filtered signal. The DC control circuit adjusts a DC voltage based on a control signal. The DC offset amplifier generates an intermediate clock based on the filtered signal and the DC voltage. The amplifier generates the output clock based on the intermediate clock. The integrator generates the control signal based on the output clock. The control signal varies with an average based on the duty cycle of the output clock.

Abstract: A mobile device includes a metal mechanism element, a ground plane, a feeding element, a parasitic element, and a dielectric substrate. The metal mechanism element has a slot. The ground plane is coupled to the metal mechanism element. The feeding element is coupled to a signal source. The feeding element extends across the slot. The parasitic element is coupled to the ground plane. The parasitic element extends across the slot. The ground plane, the feeding element, and the parasitic element are disposed on the dielectric substrate. An antenna structure is formed by the feeding element, the parasitic element, and the slot of the metal mechanism element.

Abstract: The present invention discloses a circuit capable of protecting low-voltage devices. The circuit includes: a pin configured to receive a signal of an external device; a control voltage generating circuit configured to generate a first control voltage according to a supply voltage to turn on a protected device when the supply voltage is at a high level, and generate a second control voltage according to a voltage of the pin to turn on the protected device when the supply voltage is at a low level; and the protected device configured to be turned on according to one of the first and the second control voltages and thereby electrically couple the pin with an internal circuit, in which the difference between the voltage of the pin and each of the first and the second control voltages is within a maximum withstanding voltage of the protected device.