Abstract: A semiconductor package and related methods are described. In one embodiment the semiconductor package includes a die pad, a plurality of leads, a semiconductor chip, and a package body. The die pad includes a first part that includes a lower surface and a first peripheral edge region comprising a ground region. The die pad further includes a second part that is spaced apart from the first part and that includes a lower surface and a second peripheral edge region comprising a power region. The plurality of leads is disposed around the die pad. The semiconductor chip is disposed on the die pad and is electrically coupled to the ground region, the power region, and the plurality of leads. The package body is formed over the semiconductor chip and the plurality of leads.

Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.

Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a first plurality of leads disposed in a lead placement area around the die pad, a second plurality of leads disposed in corner regions of the lead placement area, a semiconductor chip on the die pad and coupled to each lead, and a package body. Each lead includes an upper sloped portion and a lower sloped portion. An average of surface areas of lower surfaces of each of the second plurality of leads is at least twice as large as an average of surface areas of lower surfaces of each of the first plurality of leads. The package body substantially covers the upper sloped portions of the leads. The lower sloped portions of the leads at least partially extend outwardly from a lower surface of the package body.

Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a plurality of leads, a chip, and a package body. The die pad includes: (1) a peripheral edge region defining, a cavity with a cavity bottom including a central portion; (2) an upper sloped portion; and (3) a lower sloped portion. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the central portion of the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body.

Abstract: The present invention relates to an improved process for preparing high performance aliphatic-aromatic mixed waterborne polyurethanes (PUs). Waterborne PUs prepared from mixed aromatic diisocyanates and aliphatic diisocyanates exhibit superior mechanical properties as compared with those prepared from aliphatic diisocyanates alone.

Abstract: A short circuit protection device for the protection of an alternator in which turning on/off a trigger switch causes conduction/cutoff of the field current of the field coil of the alternator is disclosed. The protection device enables the field current to pass through a sensor so that when the field current is abnormally high and the voltage drop across the sensor rises, the potential of an input end of a boost circuit electrically connected to the sensor correspondingly arises and an output end of the boost circuit electrically connected to a shutoff device drives the shutoff device to turn off the trigger switch, and the boost circuit further keeps the shutoff device in on-state to hold the trigger switch off till the short circuit condition is eliminated and the protection circuit system is reset.

Abstract: The NAND flash memory device contains a NAND flash memory, a mirror data area, and a controller. The mirror data area has a size at least to hold a page of data and is usually formed by random access memory. The controller saves a data to be written into the NAND flash memory that occupies a partial number of the sectors of a first page of the NAND flash memory into the sectors of a second page of the mirror data area. When a new data is to be written into the remaining sectors of the first page of the NAND flash memory, the new data is stored instead into the second page's remaining sectors of the mirror data area. When the second page of the mirror data area is full, the entire second page is written into the first page of the NAND flash memory.

Abstract: A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

Abstract: A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.

Abstract: The present invention relates to a water dispersible polyisocyanate composition bearing urea comprising (a) an aliphatic polyisocyanate or a mixture of aliphatic polyisocyanates or a mixture of aliphatic polyisocyanates with other polyisocyanates; and (b) a reaction product of component (a) with component (c) a polyoxyalkylene amine or a mixture of a polyoxyalkylene amine and a polyoxyalkylene alcohol. The present invention also relates to a water dispersible polyisocyanate composition bearing urea and urea derivatives which is obtained by heating the above composition bearing urea for conducting a subsequent reaction, to increase the numbers of isocyanate functional groups contained in said composition, wherein the urea derivatives include biuret, triuret and tetrauret, and most of them are biuret.

Abstract: A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.

Abstract: Disclosed are a macrocyclic carbodiimide (MC-CDI) and a process for synthesizing the same through condensation of a molecule with multiple-isocyanate terminal functional groups under high dilution in the presence of a phospholene catalyst such as phospholene or arsenic catalyst. Also disclosed are MC-CDI derivatives, such as MC-urea (MC-U), MC-acylurea (MC-ACU), acid functionalized MC-ACU, and anhydride functionalized MC-ACU, processes for synthesizing the same, and the applications of such derivatives as hydrolysis stabilizers in organic polymeric materials, such as polyurethane (PU) and polyesters, as well as the applications in the syntheses of the amide- and imide-modified polyurethane by ring-opening reaction of the MC-ACU.

Abstract: An indolestyryl compound. The indolestyryl compound has formula (I): wherein Z1 comprises benzene, naphthalene, or heterocyclic ring containing O, S, or N, R2 comprises H, halogen atoms, C1-5 alkyl, nitro, ester, carboxyl, sulfo, sulfonamide, sulfuric ester, amide, C1-3 alkoxy, amino, alkylamino, cyano, C1-6 alkylsulfonyl, or C2-7 alkoxy carbonyl, R3, R4, R5, and R6 comprise H, alkyl, aralkyl, or heterocyclic ring containing O, S, or N, R7 and R8 comprise H or alkyl, R10 comprises H, alkyl, halogen atoms, nitro, hydroxyl, amino, ester, or substituted or non-substituted sulfonyl, W comprises carbon or nitrogen, Y comprises carbon, oxygen, sulfur, selenium, —NR, or —C(CH3)2, m is 1˜3, and X1 comprises an anionic group or an anionic organometallic complex, wherein R3 and R4 are joined to a nitrogen atom or R5 and R6 are joined together to form a ring, and R bonded to nitrogen is C1-5 alkyl.

Abstract: A fluorescent dye, a structure of a fluorescent storage media and method using thereof, are disclosed. The fluorescent dye of the present invention comprises an organic violet fluorescent compound having a chemical structure (I) is suitable for using a short wavelength laser having a wavelength less than 500 nm as an excitation source. When a short wavelength laser is used for exciting the organic violet fluorescent compound (I), a fluorescence having an emission wavelength larger than 500 nm is induced, and a reading signal can be provided by detecting the intensity of the fluorescence radiation.

Abstract: The present invention is related to a fuel cell combining a stack and a reformer, which comprises a stack having a coupling part and a reformer having a conjugate part. The conjugate part of the reformer may couple to the coupling part of the stack. The full cell according to the present invention reduces the volume, fully utilizes thermal energy, and reduces the use of raw materials to minimize expenses.

Abstract: A fuel cell system has a distributor, at least one catalytic converter for the reformation reaction and a stack. When the fuel cell system has more than two catalytic converters for the reformation reaction a converging chamber can be added into the system to input the hydrogen gas generated by the catalytic converter for the reformation reaction to the stack. Therefore, the present invention can integrate the catalytic converter for the reformation reaction and the stack to reduce both the cost and fuel cell volume, and save fuel.

Abstract: A bisstyryl compound. The bisstyryl compound has formula (I): wherein Z1 and Z2 are benzene, naphthalene, or heterocyclic ring, R1 is H, C1-5 alkyl, hydroxyl, halogen atoms, or alkoxy, R2 is H, halogen atoms, C1-5 alkyl, nitro, ester, carboxyl, sulfo, sulfonamide, sulfuric ester, amide, C1-3 alkoxy, amino, alkylamino, cyano, C1-6 alkylsulfonyl, or C2-7 alkoxy carbonyl, R3, R4, R5, and R6 are H, halogen atoms, alkyl, aralkyl, or heterocyclic ring containing O, S, or N, or R3 and R4 are joined to a nitrogen atom or R5 and R6 are joined together to form a ring, R7 and R8 are H or alkyl, W is nitrogen with or without Z1 and Z2 or aromatic group without Z1 and Z2, Y is carbon, oxygen, sulfur, selenium, —NR, or —C(CH3)2, m is 1-3, n is 1-18, and X1 and X2 are anionic groups or anionic organometallic complexes.

Abstract: A bis(indolestyryl) compound. The bis(indolestyryl) compound has formula (I): wherein A and B comprise benzene, naphthalene, or heterocyclic ring containing O, S, or N, R1 and R1? are H, halogen atoms, C1-5 alkyl, nitro, ester, carboxyl, sulfo, sulfonamide, amide, sulfo ester, C1-3 alkoxy, amino, alkylamino, cyano, C1-6 alkylsulfonyl, or C2-7 alkoxy carbonyl, R2, R2?, R3, and R3? comprise H, C1-6 alkyl, C6-18 aryl, C2-6 alkenyl, C3-6 cycloalkenyl, or C3-6 cycloalkyl, R4 is H, C1-5 alkyl, hydroxyl, halogen atoms, or alkoxy, R5 and R5? comprise H, halogen atoms, C1-5 alkyl, nitro, C1-3 alkoxy, amino, cyano, C1-6 alkylsulfonyl, or C2-7 alkoxy carbonyl, W comprises oxygen, sulfur, selenium, —NR, or —C(CH3)2, n is 1˜18, and Z1 and Z2 are different and comprise an anion or an anionic organometallic complex with +1 or +2 valence, wherein R bonded to nitrogen is C1-4 alkyl.

Abstract: A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.

Abstract: Each of a method for determining a parasitic capacitance and an apparatus for determining the parasitic capacitance provides for an experimental correlation within a parasitic capacitance model of a series of conductor layer nominal dimensions and spacings with a process related deviation to provide a series of conductor layer actual dimensions and spacings. The method and the apparatus further provide for determining the parasitic capacitance while employing the conductor layer actual dimensions and spacings. The parasitic capacitance is thus determined with enhanced accuracy.