Patents by Inventor Chien-Wen Chen

Chien-Wen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8397380
    Abstract: A method of manufacturing an integrated circuit package includes providing a ball grid array (BGA) module including BGA balls on a side of the BGA module; providing a base substrate; and placing the BGA module on the base substrate. The BGA balls are placed between the BGA module and the base substrate. An adhesive is applied between and contacting the BGA module and the base substrate. The adhesive is then cured. The BGA balls are re-flowed after the step of curing the adhesive.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: March 19, 2013
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., Global Unichip Corp.
    Inventors: Chia-Jen Kao, Chen-Fa Tsai, Chien-Wen Chen
  • Publication number: 20130019219
    Abstract: System and method for hierarchy reconstruction from a flattened layout are described. In one embodiment, a method for producing a reconstructed layout for an integrated circuit design from an original layout and a revised layout includes, for each pattern of the original layout, determining a pattern of the revised layout that corresponds to the pattern of the original layout; and assigning the corresponding pattern of the revised layout to a temporary instance, the temporary instance corresponding to an instance of the pattern of the original layout and citing to a temporary cell. The method further includes creating a temporary reconstructed layout from the temporary instances; and producing the reconstructed layout from the temporary reconstructed layout, wherein a hierarchy of the reconstructed layout is similar to a hierarchy of the original layout.
    Type: Application
    Filed: July 13, 2011
    Publication date: January 17, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Yu Chen, Yi-Tang Lin, Cheok-Kei Lei, Hsiao-Hui Chen, Yu-Ning Chang, Hsingjen Wann, Chih-Sheng Chang, Chien-Wen Chen
  • Publication number: 20120330440
    Abstract: A knee joint prosthesis is adapted for interconnecting a prosthetic lower leg and a prosthetic thigh. The knee joint prosthesis includes a knee seat disposed under and connected to the prosthetic thigh, a connecting seat disposed above and connected to the prosthetic lower leg, a link assembly, and an adjusting unit. The link assembly includes a plurality of links each connected pivotally to the knee seat and the connecting seat in such a manner to allow the knee joint prosthesis to change between an elevated position and a flexed position. The adjusting unit is disposed in the knee seat, and is operable to cooperate with the link assembly to adjust difficulty level of changing the knee joint prosthesis between the elevated and flexed positions.
    Type: Application
    Filed: November 30, 2011
    Publication date: December 27, 2012
    Inventors: Chien-Wen CHEN, Chien-Cheng CHEN
  • Publication number: 20120304146
    Abstract: A design system includes a layout module and a user interface. The layout module includes a computing unit, which is configured to extract layout parameters of an integrated circuit device in a circuit during a layout stage of the circuit, and calculate circuit parameters of the device using the layout parameters. The user interface is configured to display the circuit parameters of the device in response to a user selection of the device.
    Type: Application
    Filed: May 25, 2011
    Publication date: November 29, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sian Jiang, Ya-Li Tai, Mu-Jen Huang, Chien-Wen Chen, Chauchin Su
  • Publication number: 20120293220
    Abstract: A reset control device for an electronic device having a battery for providing operating power for a system circuit is provided. The reset control device includes a signal generating unit for generating a control signal, and a control module installed in the battery and coupled to the signal generating unit for disconnecting a power supply link between the battery and the system circuit for a predetermined duration and recovering the power supply link, when the control signal conforms to a predefined rule, so as to reset the system circuit.
    Type: Application
    Filed: August 22, 2011
    Publication date: November 22, 2012
    Inventors: Chuan-Yuan Li, Chien-Wen Chen
  • Publication number: 20120278777
    Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.
    Type: Application
    Filed: March 9, 2012
    Publication date: November 1, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Tang LIN, Cheok-Kei LEI, Shu-Yu CHEN, Yu-Ning CHANG, Hsiao-Hui CHEN, Chih-Sheng CHANG, Chien-Wen CHEN, Clement Hsingjen WANN
  • Publication number: 20120278776
    Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated.
    Type: Application
    Filed: March 9, 2012
    Publication date: November 1, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheok-Kei LEI, Yi-Tang LIN, Hsiao-Hui CHEN, Yu-Ning CHANG, Shu-Yu CHEN, Chien-Wen CHEN, Chih-Sheng CHANG, Clement Hsingjen WANN
  • Publication number: 20120260225
    Abstract: A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.
    Type: Application
    Filed: June 19, 2012
    Publication date: October 11, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ke-Ying Su, Chia-Ming Ho, Gwan Sin Chang, Chien-Wen Chen
  • Patent number: 8284537
    Abstract: An electronic apparatus with electrostatic discharge protection includes: a conducting casing and a circuit board. The circuit board has a power ground node and a conditional conducting path, and is set inside the conducting casing. The conditional conducting path further includes: a conducting element and an electrostatic discharging component. One end of the conducting element is electrically connected to the conducting casing, and the electrostatic discharging component is electrically connected between another end of the conducting element and the power ground node. When the voltage variation between the two ends of the electrostatic discharging element reaches a preset condition, the electrostatic discharging component functions as a short circuit; otherwise, the electrostatic discharging element is equivalent to a high impedance element. The power ground node electrically connects to an electrode of a battery for using it as a vessel of receiving electrostatic charges.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: October 9, 2012
    Assignee: Simplo Technology Co., Ltd.
    Inventor: Chien-Wen Chen
  • Patent number: 8278145
    Abstract: The present invention provides a method for packaging semiconductor device which is using more than once reflow processes to heat the solder ball to prevent the deformation of solder ball, so that the yield of the manufacturing process can be increased and the reliability of the semiconductor device can be increased.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: October 2, 2012
    Assignee: Global Unichip Corporation
    Inventors: Chien-Wen Chen, Longqiang Zu, Chen-Fa Tsai
  • Patent number: 8214784
    Abstract: A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: July 3, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ke-Ying Su, Chia-Ming Ho, Gwan Sin Chang, Chien-Wen Chen
  • Publication number: 20120108742
    Abstract: The present invention relates to a waterborne polyurethane containing biodegradable segments and the process for synthesizing the same. The waterborne polyurethane according to the present invention has excellent biodegradable, biocompatible and mechanical characteristics and thus is a useful biomedical material, in particular for making films for medical applications.
    Type: Application
    Filed: October 25, 2011
    Publication date: May 3, 2012
    Inventors: Shenghong A. Dai, Chien-Wen Chen, You-Sing Chen, Shan-Hui Hsu
  • Publication number: 20120059576
    Abstract: A method, a system, an apparatus, and a computer-readable medium for browsing spot information, adapted to an electronic device, are provided. In the present method, a plurality of spot information are retrieved, in which each of the spot information at least comprises a picture and a location of a spot. Next, an electronic map is displayed and a spot marker is marked at the spot location of each spot information on the electronic map. Meanwhile, a spot browsing bar is displayed on a side of the electronic map and the spot pictures of the spot information are sequentially displayed in the spot browsing bar. When a select operation of a certain spot marker on the electronic map is received, the spot browsing bar is scrolled to show the spot picture corresponding to the selected spot marker.
    Type: Application
    Filed: March 3, 2011
    Publication date: March 8, 2012
    Applicant: HTC CORPORATION
    Inventors: Po-Yen Lee, Chien-Wen Chen, Pai-Chang Yeh, Li-Wen Lian
  • Publication number: 20120052603
    Abstract: A method for detecting the under-fill void of the flip chip ball grid array package structure is provided, which includes providing a substrate having an interconnect structure and a plurality of interposers therein; providing a chip having an active surface and a back side, and a plurality of first connecting elements on the active surface of the chip; mounting and electrically connecting the active surface of the chip on the substrate; performing at least once IR reflow to fix the plurality of first connecting elements on the substrate; filling an encapsulate material to cover the active surface of the chip and the plurality of first connecting elements; performing a detecting process to detect that void is not formed between the active surface of the chip and the plurality of first elements; and forming a plurality of second connecting elements on the back side of the substrate to obtain a flip chip ball grid array package structure.
    Type: Application
    Filed: March 9, 2011
    Publication date: March 1, 2012
    Applicant: Global Unichip Corporation
    Inventors: Chien-Wen Chen, Chia-Jen Kao, Jui-Cheng Chuang
  • Patent number: 8120152
    Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a first plurality of leads disposed in a lead placement area around the die pad, a second plurality of leads disposed in corner regions of the lead placement area, a semiconductor chip on the die pad and coupled to each lead, and a package body. Each lead includes an upper sloped portion and a lower sloped portion. An average of surface areas of lower surfaces of each of the second plurality of leads is at least twice as large as an average of surface areas of lower surfaces of each of the first plurality of leads. The package body substantially covers the upper sloped portions of the leads. The lower sloped portions of the leads at least partially extend outwardly from a lower surface of the package body.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: February 21, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Pao-Huei Chang Chien, Ping-Cheng Hu, Chien-Wen Chen
  • Patent number: 8115285
    Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: February 14, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Wen Chen, Yi-Shao Lai, Hsiao-Chuan Chang, Tsung-Yueh Tsai, Pao-Huei Chang Chien, Ping-Cheng Hu, Hsu-Yang Lee
  • Publication number: 20120021564
    Abstract: The present invention provides a method for packaging semiconductor device which is using more than once reflow processes to heat the solder ball to prevent the deformation of solder ball, so that the yield of the manufacturing process can be increased and the reliability of the semiconductor device can be increased.
    Type: Application
    Filed: April 6, 2011
    Publication date: January 26, 2012
    Applicant: Global Unichip Corporation
    Inventors: Chien-Wen Chen, Longqiang Zu, Chen-Fa Tsai
  • Publication number: 20110293870
    Abstract: A composite cover sheet includes a first protective film, a first adhesive layer, a second protective film and a second adhesive layer. The first protective film has a first sticking part and a first movable part. The first protective film is attached to a base sheet through the first adhesive layer, and the first protective film is removed from the base sheet through the first movable part. The second protective film has a second sticking part and a second movable part, and the second protective film and the first protective film are separately formed. The second protective film is attached to the first protective film through the second adhesive layer, and the second protective film is removed from the first protective film through the second movable part.
    Type: Application
    Filed: May 23, 2011
    Publication date: December 1, 2011
    Inventors: Ming-Chuan LIN, Ping-Wen Huang, Shih-Cheng Wang, Chin-Liang Chen, Hsien-Ming Wu, Chen-Anne Chuang, Chien-Wen Chen, Hui-Chin Chen, Han-Chung Chen
  • Publication number: 20110270415
    Abstract: An artificial knee joint includes a lower joint member, an axle, a kneecap member, and a press member. The lower joint member is formed with a horizontally extending axle-receiving hole, and a clearance extending from and in spatial communication with the axle-receiving hole. The axle is received in the axle-receiving hole. The kneecap member is pivoted to the lower joint member, and is adapted to be connected to a prosthetic thigh. The press member is mounted to the kneecap member for pressing the lower joint member when the kneecap member pivots in a direction relative to the lower joint member. Therefore, the clearance and the axle-receiving hole are constricted to result in tightened connection between the lower joint member and the axle and resistance to relative rotation between the lower joint member and the axle.
    Type: Application
    Filed: April 29, 2010
    Publication date: November 3, 2011
    Inventors: Chien-Wen Chen, Chien-Cheng Chen
  • Publication number: 20110258292
    Abstract: A file download method for a mobile device, a server and a mobile device thereof, and a computer-readable medium are provided. In the method, the server obtains file identification information according to an access operation of a terminal device on a service website. When the file identification information corresponds to a file of a first type, the server transmits the file of the first type to the mobile device directly. When the file identification corresponds to a file of a second type, the server transmits the file identification information to the mobile device, so that the mobile device downloads the file of the second type according to the file identification information.
    Type: Application
    Filed: April 15, 2011
    Publication date: October 20, 2011
    Applicant: HTC CORPORATION
    Inventors: Po-Yen Lee, Chien-Wen Chen, Pai-Chang Yeh, Li-Wen Lian