Abstract: A vending method capable of supporting vending machine with identity (ID) recognition function, suitable for a vending machine for verifying an identity of a consumer, and the method comprises steps of: generating a digital information on the vending machine; enabling an identity recognition application according to the digital information; enabling an image capture unit of a mobile device through the identity recognition application to capture a current head portrait of the consumer; and determining if the consumer passing through an identity recognition by using the identity recognition application; wherein, if the consumer passes through the identity recognition, enabling a sale function of the vending machine.

Abstract: A capacitor cell is provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate connected to the first node. A second PMOS transistor is coupled between the second node and the first node, and has a gate connected to the second node. A second NMOS transistor has a drain connected to the first node, a gate connected to the first node, and a source connected to the ground or the second node. The first and second PMOS transistors and the first and second NMOS transistors are arranged in the same row. The second PMOS transistor is disposed between the first PMOS transistor and the first and second NMOS transistors.

Abstract: The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. The second-type well and the deep-second-type well form an enclosed space that includes the first-type well. The MOSFET also includes an embedded semiconductor region (ESR) in a vicinity of the enclosed space. The ESR includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.

Abstract: A 3D depth image acquiring method and apparatus, and an image acquisition device are provided. The method is applied to an image acquisition device comprising a VIS-NIR picture sensor and an infrared structured light projection component. The VIS-NIR picture sensor comprises a plurality of dot matrix units each having a blue light photosensitive component, a green light photosensitive component, a red light photosensitive component and an NIR photosensitive component distributed thereon. The method comprises: controlling the blue light photosensitive component, the green light photosensitive component, the red light photosensitive component, the NIR photosensitive component and the infrared structured light projection component to operate, to obtain an optimum NIR image and an optimum VIS image; and processing the optimum VIS image and a depth image which is obtained by performing calculation on the optimum NIR image using a 3D depth mode, to obtain a 3D depth image.

Abstract: The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. The second-type well and the deep-second-type well form an enclosed space that includes the first-type well. The MOSFET also includes an embedded semiconductor region (ESR) in a vicinity of the enclosed space. The ESR includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.

Abstract: The invention provides a system for evaluating food flavors based on a gas, including a multi-gas sensing module and an odor information processing module. The sensing module includes a colorimetric gas sensing chip for reacting with odor molecules emitted by the food to be evaluated to form a coloring reaction, and the sensing module generates a color image respectively corresponding to coloring reaction according to the coloring reaction. The processing module is communicatively connected with the sensing module and includes an image acquisition unit for converting the color image into an odor information, a database unit including a plurality of identification information, and an arithmetic unit perform a calculation to form a result for evaluating the food flavors based on the plurality of identification information and the color image. The user can judge the actual condition of foods according to the result for evaluating the food flavors.

Abstract: The present invention relates to a colorimetric sensor chip includes a chemical reaction layer and a coloring reaction layer. The chemical reaction layer includes reaction zones reacting with a gas to be tested to produce a chemical change. The coloring reaction layer includes a coloring side and a reaction side in contact with the reaction zone which are opposite to each other. The coloring reaction layer further includes a coloring indicator to produce a coloring reaction corresponding to the chemical change of the reaction sides, thereby completing a light, thin and highly integrated gas sensor chip directly attaching or placing on an object to be sensed for real-time sensing.

Abstract: A gas-sensing tattoo sticker includes an adhesive layer, a coloring reaction layer, and a chemical reaction layer, disposed by stacking. The chemical reaction layer includes reaction zones capable of reacting with a gas to be tested to produce a chemical change; the coloring reaction layer includes coloring sides and correspondingly disposed reaction sides in contact with the reaction zones, and includes a coloring indicator to produce a coloring reaction corresponding to the chemical change of the reaction sides; to and the adhesive layer is provided on a side of the coloring reaction layer or the chemical reaction layer to provide adhesion, thereby completing the gas-sensing tattoo sticker, changes of gas in the surrounding environment can be sensed when air inlet sides are outwardly adhered on an object; and the smell of an object itself can be sensed when the air inlet sides are inwardly adhered on the object.

Abstract: The invention provides a system for managing food information based on an odor, which comprises a gas sensing module, a processing module, a blockchain module and a display module. The gas sensing module includes a colorimetric gas sensing chip reacting with odor molecules emitted by the food to form a coloring reaction and present a color image corresponding to the food. The processing module includes a conversion unit for converting the color image into identification information corresponding to the food. The blockchain module includes a plurality of nodes, and the plurality of nodes store identification information corresponding to the food. The display module includes an identification label corresponding to the identification information. Therefore, when the invention is applied to the blockchain technology, it can remove the doubt that the data on the chain can be falsified before the data is uploaded.

Abstract: A semiconductor device includes a first well, a first region and fourth regions of a first conductivity type as well as second regions, a third region, a second well of the second conductivity type. A first region is disposed in the first well and coupled to a first reference voltage terminal. Second regions are disposed in the first well, wherein one of the second regions is coupled to the first reference voltage terminal, and the second regions and the first well are included in a first transistor. A third region is disposed in the first well. A first resistive load is coupled between the third region and a second reference voltage terminal. A second well is coupled to the first well. Fourth regions are disposed in the second well, wherein the second well and at least one of the fourth regions are included in a second transistor.

Abstract: Disclosed are a CMOS image sensor encapsulation structure and a method for manufacturing the same, including the steps of: firstly, a transparent substrate material is fixed to a surface of a first insulating layer having a micro convex lens, a dummy wafer is fixed on a surface of the transparent substrate material, and then a wafer is thinned by grinding, and in this process, the transparent substrate material provides more mechanical support force for the wafer, therefore, the wafer can become thinner by grinding, thus the CMOS image sensor encapsulation structure is characterized by being formed in a thin shape. Besides, a second installation area has a protection glue layer which can prevent oxygen and moisture from entering internal elements and absorb scattered light.

Abstract: A CMOS image sensor encapsulation structure and its manufacturing method, including: forming a blind hole in a combined layer formed by a first insulating layer and a wafer, a surface of the first insulating layer facing away from the wafer having a micro convex lens; forming a second insulating layer on a hole wall of the blind hole, then filling an electrically conductive material in the blind hole having the second insulating layer, and making a conductor in the combined layer in signal connection with the micro convex lens and an IC extend to a surface of the first insulating layer and electrically connecting the conductor to the electrically conductive material; fixing the transparent substrate material on a surface of the first insulating layer having the micro convex lens, forming a dummy wafer on a surface of the transparent substrate material, and then thinning the wafer by grinding.

Abstract: A circuit includes a first transistor, a second transistor and a first resistive load. The first transistor has a first terminal coupled to a first reference voltage terminal, a second terminal coupled to a second reference voltage terminal, and a control terminal coupled to the first reference voltage terminal. The second transistor has a first terminal coupled to the second reference voltage terminal, a second terminal coupled to the first reference voltage terminal and the control terminal of the first transistor, and a control terminal coupled to the second reference voltage terminal and the second terminal of the first transistor. The first transistor further comprises a third terminal coupled to the second reference voltage terminal through the first resistive load.

Abstract: A manufacturing method of nitrogenous carbon electrode and flow cell provided therewith is disclosed. Firstly, a preformed body is performed by mixing a carbon material, a polymeric material and a modifier. A formation process is performed on the preformed body to obtain a formed body. A high sintering is then performed, such that a part of the polymeric material is decomposed and then removed, while the other part of polymeric material is cooperated with the carbon material to form a skeletal structure including a plurality of pores, and that the nitrogen in the modifier is adhered to the skeletal structure to form a nitrogenous functional group, and then form a nitrogenous carbon electrode. The nitrogenous carbon electrode may be applied to the flow cell. Thereby, electric conductivity in a vertical direction may be enhanced, so as to reduce internal resistance of the flow cell and increase discharge power.

Abstract: A capacitor cell is provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate connected to the first node. A second PMOS transistor is coupled between the second node and the first node, and has a gate connected to the second node. A second NMOS transistor has a drain connected to the first node, a gate connected to the first node, and a source connected to the ground or the second node. The first and second PMOS transistors and the first and second NMOS transistors are arranged in the same row. The second PMOS transistor is disposed between the first PMOS transistor and the first and second NMOS transistors.

Abstract: A capacitor cell is provided. A first PMOS transistor is coupled between a power supply and a first node, having a gate coupled to a second node. A first NMOS transistor coupled between a ground and the second node, having a gate coupled to the first node. A second PMOS transistor, having a drain coupled to the second node, a gate coupled to the second node, and a source coupled to the power supply or the first node. A second NMOS transistor, having a drain coupled to the first node, a gate coupled to the first node, and a source coupled to the ground or the second node.

Abstract: A living organism image monitoring system is provided, relating to the technical field of medical equipment. The living organism image monitoring system comprises a display module, a processor and a CIGS chip, the CIGS chip, the processor and the display module being electrically connected, the CIGS chip being used for detecting a near infrared light signal of a living organism and generating a current signal after having detected the near infrared light signal, the processor being used for generating a first pulse signal according to the current signal, and the display module being used for displaying an image according to the first pulse signal. The living organism image monitoring system provided by the present disclosure has the advantages of being capable of synchronously transmitting the images of a living organism to the display module for display and enabling the images to be clearer.

Abstract: A 3D depth image acquiring method and apparatus, and an image acquisition device are provided. The method is applied to an image acquisition device comprising a VIS-NIR picture sensor and an infrared structured light projection component. The VIS-NIR picture sensor comprises a plurality of dot matrix units each having a blue light photosensitive component, a green light photosensitive component, a red light photosensitive component and an NIR photosensitive component distributed thereon. The method comprises: controlling the blue light photosensitive component, the green light photosensitive component, the red light photosensitive component, the NIR photosensitive component and the infrared structured light projection component to operate, to obtain an optimum NIR image and an optimum VIS image; and processing the optimum VIS image and a depth image which is obtained by performing calculation on the optimum NIR image using a 3D depth mode, to obtain a 3D depth image.

Abstract: Disclosed are a CMOS image sensor encapsulation structure and a method for manufacturing the same, including the steps of: firstly, a transparent substrate material is fixed to a surface of a first insulating layer having a micro convex lens, a dummy wafer is fixed on a surface of the transparent substrate material, and then a wafer is thinned by grinding, and in this process, the transparent substrate material provides more mechanical support force for the wafer, therefore, the wafer can become thinner by grinding, thus the CMOS image sensor encapsulation structure is characterized by being formed in a thin shape. Besides, a second installation area has a protection glue layer which can prevent oxygen and moisture from entering internal elements and absorb scattered light.

Abstract: A CMOS image sensor encapsulation structure and its manufacturing method, including : forming a blind hole in a combined layer formed by a first insulating layer and a wafer, a surface of the first insulating layer facing away from the wafer having a micro convex lens; forming a second insulating layer on a hole wall of the blind hole, then filling an electrically conductive material in the blind hole having the second insulating layer, and making a conductor in the combined layer in signal connection with the micro convex lens and an IC extend to a surface of the first insulating layer and electrically connecting the conductor to the electrically conductive material; fixing the transparent substrate material on a surface of the first insulating layer having the micro convex lens, forming a dummy wafer on a surface of the transparent substrate material, and then thinning the wafer by grinding.