Abstract: A computing environment determines whether one or more file systems associated with an application allow for modification of a file access time of an associated file and whether a kernel updates, in at least one case, the file access time upon accessing the associated file. The associated file is at least one file managed by the one or more file systems. The computing environment determines files accessed by the application using a technique selected based on whether the one or more file systems allow for modification of the file access time or whether the kernel updates, in the at least one case, the file access time upon accessing the associated file. The computing environment provides an output representing the files accessed by the application.

Abstract: A flat panel active-matrix or passive-matrix display includes: a single back substrate divided into multiple electrically isolated or non-isolated, separately addressable, functional display sections, a set of source signal lines defining a set of columns, a set of gate signal lines defining a set of rows, and a set of pixel cells arranged in a matrix of rows and columns. Each pixel cell is addressable by a corresponding SG pair which includes a source signal line and a gate signal line, at least a first source driver circuit coupled to a first portion of the source signal lines corresponding to a first display section and a second source driver circuit coupled to a second portion of the source signal lines corresponding to a second display section. At least a first gate driver circuit is coupled to a first portion of the gate signal lines.

Abstract: A lens assembly, in sequence from an object side to an image side, includes an optical element including a plurality of pairs of nanostructures, and an image sensing element including a plurality of pairs of pixel areas. Each pair of nanostructures includes a first view nanostructure and a second view nanostructure. Each pair of pixel areas includes a first view pixel area and a second view pixel area. The first view nanostructure guides a light from the object to form an image of the object on the first view pixel area and the second view nanostructure guides a light from the object to form an image of the object on the second view pixel area.

Abstract: A LDMOS is provided in the present invention, including multiple fins spaced apart, wherein each fin has a recess region, a shallow trench isolation in those recess regions forms a thick oxide layer, a gate crosses over those fins, wherein the thick oxide layer is close to one side of the gate and partially overlaps the gate, and a source and a drain respectively at two sides of the gate in each fin, wherein the thick oxide layer extends outside the gate to the drains.

Abstract: The invention provides a static random access memory structure, which comprises a silicon substrate, a shallow trench isolation on the silicon substrate, a first fin structure connected with the silicon substrate and protruding from the shallow trench isolation, a first gate structure spanning the first fin structure and parts of the shallow trench isolation, so that the first gate structure covers a top surface and a part of sidewalls of the first fin structure, and forms a pass gate transistor (PG). And a protruding part located directly below the first gate structure and on the shallow trench isolation, the protruding part covers part of the surface of at least one sidewall of the first fin structure, and a top surface of the protruding part is higher than a top surface of the shallow trench isolation.

Abstract: A pressure generating device includes a tank, a deformable membrane, a driving device, and a connection unit. The tank defines a chamber therein, and includes an opening and a communication port each of which is in fluid communication with the chamber. The deformable membrane is disposed to seal the opening. The driving device includes a driving shaft having an end which confronts the deformable membrane. The connection unit is configured to couple the driving shaft with the deformable membrane and to permit the deformable membrane to be driven by the driving shaft to transform between a flat state and a deformed state. A detecting system including the pressure generating device for detecting quality of a test sample is also provided.

Abstract: A semiconductor package includes an interposer structure, a first semiconductor die, semiconductor dies, a first molding layer, and an encapsulant. The first semiconductor die and the second semiconductor dies are located over and electrically coupled to the interposer structure. The second semiconductor dies are laterally disposed adjacent to the first semiconductor die that includes memory dies and at least one dummy die. The first molding layer laterally surrounds the at least one dummy die. The encapsulant is disposed on the interposer structure and encapsulates the first semiconductor die and the second semiconductor dies. The first molding layer is disposed between at least one dummy die and the encapsulant. The dimensions of the memory die are substantially equal to the total dimensions of each of the at least one dummy die and the first molding layer.

Abstract: A method includes receiving a physical circuit design file that includes physical circuit partitions that are each mapped to a respective chip. The physical circuit partitions are connected to one another by a respective timing path having an original delay. The method further includes determining a slack budget of the respective timing path, and determining a delay upper bound value based on a shortest timing path delay and the slack budget. Further, the method includes updating the delay upper bound of the respective timing path based on the slack budget, assigning an interconnection delay upper bound to a physical interconnection between at least two chips based on the updated slack budget of the respective timing path, determining a multiplexing data ratio (XDR) based on at least the interconnection delay upper bound of the physical interconnection, and performing routing between the at least two chips based on the XDR.

Abstract: A computer sets an access time for a set of files to an initial value. Upon accessing a file by a set of executables, the computer sets the access time of the file to a new value. The computer identifies, from the set of files, a subset of files accessed by the set of executables based on the access time of files in the subset being different from the initial value. The computer provides an output representing the subset of files.

Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.

Abstract: A die bonding tool includes a bond head that secures a semiconductor die against a planar surface of the bond head, an actuator system that moves the bond head and the semiconductor die towards a surface of a target substrate, and at least one contact sensor configured to detect an initial contact between a first region of the semiconductor die and the surface of the target substrate, where in response to detecting the initial contact between the semiconductor die and the target substrate, the actuator tilts the planar surface of the bond head and the semiconductor die to bring a second region of the semiconductor die into contact with the surface of the target substrate and thereby provide improved contact between the semiconductor die and the target substrate and more effective bonding including instances where the planar surface of the bond head and the target substrate surface are not parallel.

Abstract: A computer sets an access time for a set of files to an initial value. Upon accessing a file by a set of executables, the computer sets the access time of the file to a new value. The computer identifies, from the set of files, a subset of files accessed by the set of executables based on the access time of files in the subset being different from the initial value. The computer provides an output representing the subset of files.

Abstract: A driving circuit for driving a synchronous rectification transistor includes a first comparator, a second comparator, a third comparator, and a gate driving circuit. When the voltage of the drain terminal of the synchronous rectification transistor is less than a first threshold, the first comparator enables a first comparison signal. When the voltage of the drain terminal is not less than a second threshold, the second comparator enables a second comparison signal. When the voltage of the drain terminal is not less than a third threshold, the third comparator enables a third comparison signal. The gate driving circuit provides a gate voltage to a gate terminal of the synchronous rectification transistor based on the first comparison signal, the second comparison signal, and the third comparison signal.

Abstract: Static random-access memory devices are provided. The static random-access memory device includes a first static random-access memory cell, a second static random-access memory cell adjacent to the first static random-access memory cell, an isolation structure between the first and second static random-access memory cells, a first dummy gate structure and a second dummy gate structure. The first dummy gate structure and the second dummy gate structure are on the isolation structure, between the first and second static random-access memory cells, and disposed along a first direction. A width of the isolation structure along the first direction is greater than or equal to a distance between a first sidewall of the first dummy gate structure facing away from the second dummy gate structure and a second sidewall of the second dummy gate structure facing away from the first dummy gate structure along the first direction.

Abstract: A die bonding tool includes a bond head that secures a semiconductor die against a planar surface of the bond head, an actuator system that moves the bond head and the semiconductor die towards a surface of a target substrate, and at least one contact sensor configured to detect an initial contact between a first region of the semiconductor die and the surface of the target substrate, where in response to detecting the initial contact between the semiconductor die and the target substrate, the actuator tilts the planar surface of the bond head and the semiconductor die to bring a second region of the semiconductor die into contact with the surface of the target substrate and thereby provide improved contact between the semiconductor die and the target substrate and more effective bonding including instances where the planar surface of the bond head and the target substrate surface are not parallel.

Abstract: A method of fabricating a semiconductor device includes recessing an upper portion of a first dielectric layer disposed over a conductive feature. The method includes filling the recessed upper portion with a second dielectric layer to form a void embedded in the second dielectric layer. The method includes etching the second dielectric layer and the first dielectric layer to form a contact opening that exposes at least a portion of the conductive feature using the void to vertically align at least a lower portion of the contact opening with the conductive feature. The method includes filling the contact opening with a conductive material to form a contact feature electrically coupled to the conductive feature.

Abstract: A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are shifted to align and connect to the power rail and the ground rail of the other one of the standard cells.

Abstract: A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are extended in width or length to connect to the power rail and the ground rail of the other one of the standard cells.

Abstract: The invention provides a semiconductor structure, which comprises a first standard cell and a second standard cell located on a substrate, wherein an isolation region is included between the first standard cell and the second standard cell, and a boundary of the first standard cell aligns with a boundary of the isolation region, a plurality of fin structures and a plurality of gates form a plurality of transistors, which are respectively located in the first standard cell and the second standard cell, and a plurality of single diffusion breaks (SDBs) located in the first standard cell and the second standard cell. A plurality of first dummy grooves in the first standard cell and the second standard cell, and a plurality of second dummy grooves in the isolation region, wherein some of the second dummy grooves overlap the first dummy grooves.

Abstract: The invention provides a semiconductor structure, which comprises a first standard cell and a second standard cell located on a substrate, wherein an isolation region is included between the first standard cell and the second standard cell, a plurality of fin structures and a plurality of gates form a plurality of transistors, which are respectively located in the first standard cell and the second standard cell, and a plurality of single diffusion breaks (SDBs) located in the first standard cell and the second standard cell. A plurality of first dummy grooves in the first standard cell and the second standard cell, and a plurality of second dummy grooves in the isolation region, wherein some of the second dummy grooves overlap the first dummy grooves.