Patents by Inventor Chih-An Huang

Chih-An Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11855232
    Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Patent number: 11854848
    Abstract: A container includes a container body and an air processing system. The container body includes a plurality of walls defining an interior space for receiving wafers. The air processing system is attached to the container body. The air processing system includes an exchange module, an air extraction module, a first contaminant removal module, a processing module, a second contaminant removal module, a controller module and a power module. The exchange module is coupled to one of the walls of the container body. The air extraction module extracts air from the container body. The first contaminant removal module is coupled to the air extraction module and the exchange module. The processing module is coupled to the air extraction module. The second contaminant removal module is coupled to the processing module and the exchange module. The controller module is configured to turn the air extraction module on and off.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: You-Cheng Yeh, Mao-Chih Huang, Yen-Ching Huang, Yu Hsuan Chuang, Tai-Hsiang Lin, Jian-Shian Lin
  • Publication number: 20230409854
    Abstract: Systems and methods of conducting a bar code scan using an imaging-based bar code scan device are provided. In one exemplary embodiment, a method is performed by an imaging-based bar code device that includes processing circuitry, an optical lens assembly having an image sensor and an optical lens with a focused region at a certain distance in front of the optical lens along an optical axis of the optical lens, a plurality of light emitting elements configured proximate the optical lens and laterally offset from the optical axis. The method includes sending, by the processing circuitry, to each light emitting element, an indication to enable that light emitting element to project a light beam towards the optical axis in the focused region so that the light beams overlap when a target bar code is in the focused region and nonoverlap when a target bar code is outside the focused region.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 21, 2023
    Applicant: Toshiba Global Commerce Solutions, Inc.
    Inventors: Wei-Yi Hsuan, Yi-Sheng Lee, Te-Chia Tsai, Chih-Huang Wang
  • Patent number: 11847852
    Abstract: A fingerprint sensor includes a die, a plurality of conductive structures, an encapsulant, a plurality of conductive patterns, a first dielectric layer, a second dielectric layer, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The conductive patterns are over the die and are electrically connected to the die and the conductive structures. Top surfaces of the conductive patterns are flat. The first dielectric layer is over the die and the encapsulant. A top surface of the first dielectric layer is coplanar with top surfaces of the conductive patterns. The second dielectric layer covers the first dielectric layer and the conductive patterns. The redistribution structure is over the rear surface of the die.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: December 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ying-Cheng Tseng
  • Patent number: 11842993
    Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Cheng Tseng, Yu-Chih Huang, Chih-Hsuan Tai, Ting-Ting Kuo, Chi-Hui Lai, Ban-Li Wu, Chiahung Liu, Hao-Yi Tsai
  • Publication number: 20230397503
    Abstract: Provided is a ferromagnetic free layer, comprising Fe, Co, B and an additive metal, and based on a total atomic number of the ferromagnetic free layer, a content of Co is more than 0 at % and less than 30 at %, a content of B is more than 10 at % and less than or equal to 35 at %, and a content of the additive metal is more than or equal to 2 at % and less than 10 at %; the additive metal comprises Mo, Re or a combination thereof, and a thickness of the ferromagnetic free layer is more than or equal to 1.5 nm and less than 2.5 nm. The ferromagnetic free layer can be applied to a MTJ structure as a single layer, and has sufficient thermal stability for maintaining good magnetic properties after thermal treatment, which makes sure that the MTJ structure can exert normal recording function.
    Type: Application
    Filed: July 27, 2022
    Publication date: December 7, 2023
    Inventors: CHIH-WEN TANG, Chih-Huang LAI, Wei-Chih HUANG, Chun-Liang YANG, Kuan-Ling OU
  • Publication number: 20230395490
    Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.
    Type: Application
    Filed: August 2, 2023
    Publication date: December 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20230397511
    Abstract: A dielectric isolation layer having a top surface may be formed over a substrate. A heater line, a phase change material (PCM) line, and an in-process conductive barrier plate may be formed over the dielectric isolation layer. An electrode material layer may be formed over the in-process conductive barrier plate. The electrode material layer and the in-process conductive barrier plate may be patterned such that patterned portions of the in-process conductive barrier plate include a first conductive barrier plate contacting a first area of a top surface of the PCM line, and a second conductive barrier plate contacting a second area of the top surface of the PCM line, and patterned portions of the electrode material layer include a first electrode contacting the first conductive barrier plate and a second electrode contacting the second conductive barrier plate.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: Harry-Hak-Lay Chuang, Chia Wen Liang, Chang-Chih Huang, Han-Yu Chen, Kuo-Chyuan Tzeng, Tsung-Hao Yeh
  • Patent number: 11835864
    Abstract: An overlay mark includes a first, a second, a third, and a fourth component. The first component is located in a first region of the first overlay mark and includes a plurality of gratings that extend in a first direction. The second component is located in a second region of the first overlay mark and includes a plurality of gratings that extend in the first direction. The third component is located in a third region of the first overlay mark and includes a plurality of gratings that extend in a second direction different from the first direction. The fourth component is located in a fourth region of the first overlay mark and includes a plurality of gratings that extend in the second direction. The first region is aligned with the second region. The third region is aligned with the fourth region.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Ching Lee, Te-Chih Huang, Yu-Piao Fang
  • Patent number: 11834880
    Abstract: A thinned hinge includes a rotating part and a torsion supply part. The rotating part includes a base and two movable members arranged on the base, the base includes two tracks for the movable members to displace along arc-shaped trajectories to generate opening and closing actions, and ends of the two movable members where extend outward from the two tracks are provided with driving members. The torsion supply part supplies torsion required by the rotating part, the torsion supply part includes a support, two rotating shafts arranged in parallel on the support, and an idle gear arranged between the two rotating shafts, the two rotating shafts are provided with connecting pieces assembled with the driving members to enable the torsion supply part and the rotating part to simultaneously act and gears engaged with the idle gear, and the gears and the idle gear are crossed helical gear structures.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: December 5, 2023
    Assignee: SINHER TECHNOLOGY INC.
    Inventors: Chih-Huang Peng, Nan-Hai Lai
  • Publication number: 20230389449
    Abstract: A dielectric isolation layer having a planar top surface is formed over a substrate. A first electrode and a second electrode are formed over the planar top surface. An insulating matrix layer is formed around the first electrode and the second electrode. A phase change material (PCM) line is formed over the insulating matrix layer. A first end portion of the PCM line contacts a top surface of the first electrode and a second end portion of the PCM line contacts a top surface of the second electrode. A dielectric encapsulation layer is formed on sidewalls of the PCM line and over the PCM line and over a top surface of the insulating matrix layer. A heater line is formed prior to, or after, formation of the PCM line. The heater line underlies the PCM line or overlies the PCM line. A PCM switch device may be provided.
    Type: Application
    Filed: May 27, 2022
    Publication date: November 30, 2023
    Inventors: Tsung-Hsueh Yang, Chang-Chih Huang, Fu-Ting Sung, Kuo-Chyuan Tzeng
  • Patent number: 11829463
    Abstract: Provided is an electronic device, including a housing, a fixing hole, a platform and a sensor. The fixing hole is located at the housing and configured to detachably fix an identification element. The platform extends outward from the lower edge of the fixing hole. The sensor is disposed on the platform and configured to communicate with the identification element.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: November 28, 2023
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chia-Hao Hung, Ming-Chih Huang, Tong-Shen Hsiung, Meng-Chu Huang, Fu-Yu Cai, Chieh Mii, Ya-Yun Huang, Minseong Kim, Shang-Chih Liang
  • Patent number: 11829314
    Abstract: A charging system includes a source terminal and a sink terminal. The control method of the charging system includes transmitting a bus voltage by the source terminal, determining whether the sink terminal has entered a sink attached state when the sink terminal receives the bus voltage, enabling a message transceiver of the sink terminal if the sink terminal has entered the sink attached state, transmitting a source message to the transceiver of the sink terminal by the source terminal, transmitting a request message to the source terminal by the message transceiver of the sink terminal while the source terminal transmits the source message, and continuing to enable a communication function for communicating with the sink terminal and continuing to transmit the bus voltage to the sink terminal by the source terminal when the source terminal receives the request message.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: November 28, 2023
    Assignee: RICHTEK TECHNOLOGY CORP.
    Inventors: Tzu-Hsuan Tseng, Tzu-Hsien Chuang, Sheng-Chun Lin, Hao-Chun Yang, Chien-Chih Huang, Heng-Min Chang, Tsung-Jung Wu, Yen-Tung Hung
  • Patent number: 11830796
    Abstract: A circuit substrate includes a base substrate, a plurality of conductive vias, a first redistribution circuit structure, a second redistribution circuit structure and a semiconductor die. The plurality of conductive vias penetrate through the base substrate. The first redistribution circuit structure is located on the base substrate and connected to the plurality of conductive vias. The second redistribution circuit structure is located over the base substrate and electrically connected to the plurality of conductive vias, where the second redistribution circuit structure includes a plurality of conductive blocks, and at least one of the plurality of conductive blocks is electrically connected to two or more than two of the plurality of conductive vias, and where the base substrate is located between the first redistribution circuit structure and the second redistribution circuit structure.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: November 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Chen, Yu-Chih Huang, Chih-Hao Chang, Po-Chun Lin, Chun-Ti Lu, Chia-Hung Liu, Hao-Yi Tsai
  • Patent number: 11830781
    Abstract: A package structure includes an insulating encapsulation, at least one die, and conductive structures. The at least one die is encapsulated in the insulating encapsulation. The conductive structures are located aside of the at least one die and surrounded by the insulating encapsulation, and at least one of the conductive structures is electrically connected to the at least one die. Each of the conductive structures has a first surface, a second surface opposite to the first surface and a slant sidewall connecting the first surface and the second surface, and each of the conductive structures has a top diameter greater than a bottom diameter thereof, and wherein each of the conductive structures has a plurality of pores distributed therein.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: November 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, Chih-Hua Chen, Ching-Hua Hsieh, Hsiu-Jen Lin, Yu-Chih Huang, Yu-Peng Tsai, Chia-Shen Cheng, Chih-Chiang Tsao, Jen-Jui Yu
  • Publication number: 20230375952
    Abstract: Cleaning equipment for an EUV wafer chuck or clamp, which removes particles that have accumulated between burls on the surface of the wafer chuck. The equipment includes a spinning bi-polar electrode placed in proximity to the surface, which can attract and adsorb the charged particle residue therefrom using its generated symmetric electric field when the wafer chuck is not in use.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 23, 2023
    Inventors: Yu-Chih HUANG, Yu-Kai CHIOU, Chieh-Jen CHENG, Li-Jui CHEN
  • Publication number: 20230375013
    Abstract: Disclosed herein is a joint structure of a telescopic cylinder, the joint structure including a telescopic unit, an extension unit and a first fixing unit, wherein the telescopic unit includes a first main body, a first combined structure and at least one first fixing structure; the extension unit includes a second main body, a second combined structure and at least one second fixing structure; the first combined structure is screwed to the second combined structure; and the first fixing unit includes at least one first fixing body, and the first fixing body is simultaneously arranged in the first fixing structure and the second fixing structure and interferes with the first main body and the second main body so as to prevent the first combined structure and the second combined structure from spiral movement.
    Type: Application
    Filed: May 2, 2023
    Publication date: November 23, 2023
    Inventors: CHIH-HUANG WANG, TIEN-NI CHENG
  • Publication number: 20230366248
    Abstract: A pivoting device, including a hinge assembly and at least two support plates. The hinge assembly includes a base, two movable members on the base, at least two fixed members connecting the movable members, and two driven levers on the base and driven by the fixed members; the base has at least two rails where the movable members are provided, the movable members enable a flexible display to be folded when moving in an arc-shaped path, and the fixed members each have an oblique slot allowing one driven lever to move therein. The support plates each have a sliding rail portion at an end thereof and allowing one driven lever to slide therein, and when the driven levers are slide along the sliding rail portion and the oblique slot simultaneously, the support plates are flipped up and tilt outwards.
    Type: Application
    Filed: May 2, 2023
    Publication date: November 16, 2023
    Inventors: Feng Yu CHUNG, Chih Huang PENG, Nan Hai LAI
  • Publication number: 20230358926
    Abstract: An optical image lens assembly includes a plurality of optical lens elements. The optical lens elements include a plurality of plastic optical lens elements having refractive power and aspheric surfaces. The plastic optical lens elements are formed by an injection molding method and include at least one defined-wavelength light absorbing optical lens element, and the defined-wavelength light absorbing optical lens element includes at least one defined-wavelength light absorbent.
    Type: Application
    Filed: April 27, 2023
    Publication date: November 9, 2023
    Inventors: Yeo-Chih HUANG, Pei-Chi CHANG, Chun-Hung TENG
  • Publication number: 20230359133
    Abstract: A semiconductor substrate stage for carrying a substrate is provided. The semiconductor substrate stage includes a base layer, a magnetic shielding layer disposed on the base layer, a carrier layer disposed on the magnetic shielding layer, a receiver disposed on the carrier layer, a storage layer disposed between the base layer and the magnetic shielding layer, and a magnetic shielding element disposed on the carrier layer and surrounding the receiver.
    Type: Application
    Filed: July 13, 2023
    Publication date: November 9, 2023
    Inventors: Yu-Huan CHEN, Yu-Chih HUANG, Ya-An PENG, Shang-Chieh CHIEN, Li-Jui CHEN, Heng-Hsin LIU