Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed directly on an upper surface of the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

Abstract: The present disclosure, in some embodiments, relates an integrated chip. The integrated chip includes a substrate. A through-substrate-via (TSV) extends through the substrate. A dielectric liner separates the TSV from the substrate. The dielectric liner is along one or more sidewalls of the substrate. The TSV includes a horizontally extending surface and a protrusion extending outward from the horizontally extending surface. The TSV has a maximum width along the horizontally extending surface.

Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.

Abstract: This disclosure relates to a method for fabricating a vapor chamber. The method includes positioning a capillary structure on a first cover, forming an accommodation space, a flow channel, and a plurality of posts on a first surface of a second cover, covering the first cover with the second cover, positioning the first cover and the second cover such that the plurality of posts are spaced apart from the capillary structure by a distance, and pressure welding the first cover and the second cover so as to form a chamber between the first cover and second cover and a passage connected to the chamber and to pressure weld the plurality of posts with the capillary structure.

Abstract: A semiconductor device includes a substrate, a body structure and an electronic component. The body structure is disposed above the substrate and includes a semiconductor die, a molding compound, a conductive component and a lower redistribution layer (RDL). The semiconductor die has an active surface. The molding compound encapsulates the semiconductor die and has a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.

Abstract: A semiconductor package structure includes a first redistribution layer, a semiconductor die, a thermal spreader, and a molding material. The semiconductor die is disposed over the first redistribution layer. The thermal spreader is disposed over the semiconductor die. The molding material surrounds the semiconductor die and the thermal spreader.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure over a substrate. The semiconductor structure also includes source/drain structures on opposite sides of the gate structure. The semiconductor structure also includes a dielectric layer over the gate structure and the source/drain structures. The semiconductor structure also includes a via plug passing through the dielectric layer and including a first group IV element. The dielectric layer includes a second group IV element, a first compound, and a second compound, and the second compound includes elements in the first compound and the first group IV element.

Abstract: A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.

Abstract: An integrated circuit (IC) chip assembly includes an integrated circuit (IC) die that includes a first substrate in which plurality of transistors is formed, a first structure that contains a plurality of first metallization components, and a second structure that contains a plurality of second metallization components. The first structure is disposed over a first side of the first substrate. The second structure is disposed over a second side of the first substrate opposite the first side. The chip assembly includes a second substrate bonded to the IC die through the second side. The chip assembly includes a trench that extends through the second substrate and through the second structure of the IC die. Sidewalls of the trench are defined at least in part by one or more protective layers.

Abstract: A semiconductor substrate includes a plurality of transistors. A first structure is disposed over a first side of the semiconductor substrate. The first structure contains a plurality of first metallization components. A carrier substrate is disposed over the first structure. The first structure is located between the carrier substrate and the semiconductor substrate. One or more openings extend through the carrier substrate and expose one or more regions of the first structure to the first side. A second structure is disposed over a second side of the semiconductor substrate opposite the first side. The second structure contains a plurality of second metallization components.

Abstract: An underwater ultrasonic device includes a curvilinear ultrasonic transducer and a plurality of straight linear ultrasonic transducers. The straight linear ultrasonic transducers are disposed with respect to the curvilinear ultrasonic transducer. A first angle is included between the straight linear ultrasonic transducers. One of the curvilinear ultrasonic transducer and the straight linear ultrasonic transducer is configured to transmit a plurality of ultrasonic signals. Another one of the curvilinear ultrasonic transducer and the straight linear ultrasonic transducer is configured to receive a plurality of reflected signals of the ultrasonic signals.

Abstract: A bicycle torque detector includes a crank shaft formed with a first ring section and a second ring section; the first ring section serving for receiving a deformation sleeve accommodating ring and a deformable sleeve; the second ring section serving for receiving a circuit board ring; a circular casing serving to enclose all the crank shaft, the elastic ring, the sleeve, and the circuit board ring; wherein the first ring section of the crank shaft is formed with at least one resisting portion; the deformable sleeve has at least one resisting portion; the resisting portion of the crank shaft resists against one end of the deformation sleeve accommodating ring; another end of the deformation sleeve accommodating ring resists against the resisting portions of the deformable sleeve. A rear end of the deformable sleeve is engaged to a chain sleeve. The deformation sleeve accommodating ring is adhesive with sensing sheet.

Abstract: An embodiment of the present disclosure provides an online integrated microcontroller development tool system. Through the present disclosure, a microcontroller block of a suitable model number is selected according to a client requirement, pins of the microcontroller may be arranged, the microcontroller block with the arranged have been pins is connected to a functional component selected by the client, a corresponding circuit structure is generated, and based on the circuit structure, a microcontroller system hardware description code is generated and output. Different from the conventional development platform, the present disclosure helps clients to develop microcontroller application circuits for different applications through a pin required module, a functional component module and a description code project output module. Thus, purposes of simple operation and saving development time can be achieved.

Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and a memory die are mounted on a top surface of the bottom substrate in a side-by-side fashion. The logic die may have a thickness not less than 125 micrometers. A connection structure is disposed between the bottom substrate and the top substrate around the logic die and the memory die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and sealing the logic die, the memory die, and the connection structure in the gap.

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate structure, and source/drain structures. The semiconductor fin extends upwardly from the substrate. The gate structure is across the semiconductor fin and includes a high-k dielectric layer over the semiconductor fin, a fluorine-containing work function layer over the high-k dielectric layer and comprising fluorine, a tungsten-containing layer over the fluorine-containing work function layer, and a metal gate electrode over the tungsten-containing layer. The source/drain structures are on the semiconductor fin and at opposite sides of the gate structure.

Abstract: A spherical screen module unit includes a sector base including a sector carrier having an inner and outer arc edges; arc length of the outer arc edge is greater than that of the inner arc edge. An inner ramp frame is on the sector carrier and closer to the inner arc edge; an outer ramp frame is on the sector carrier and closer to the outer arc edge. When the spherical screen module unit is on a spherical screen assembling surface, minimum distance between the inner ramp frame upper surface and the spherical screen assembling surface is first height; maximum distance between the outer ramp frame upper surface and the spherical screen assembling surface is second height which is greater than the first height. A spherical screen structure including spherical screen module unit facilitates the module unit disassembly for repair, maintenance, or angle adjustment, and increases applicability in different environments.

Abstract: A highly efficient light extraction system for LED chip arrays, in which a multi-function domed lens overlays the LED chip array. A lower portion of the multi-function domed lens acts as a reflector, capturing wide-angle light emitted by the LED chips. An upper portion of the multi-function domed lens provides the function of a refractive lens. The multi-function domed lens provides improved light extraction efficiency over prior art embodiments, greater total light output, as well as a narrower light distribution pattern, with increased light intensity at the center of the beam.

Abstract: A bicycle torque detector includes a crank shaft formed with a first ring section and a second ring section; the first ring section serving for receiving a deformation sleeve accommodating ring and a deformable sleeve; the second ring section serving for receiving a circuit board ring; a circular casing serving to enclose all the crank shaft, the elastic ring, the sleeve, and the circuit board ring; wherein the first ring section of the crank shaft is formed with at least one resisting portion; the deformable sleeve has at least one resisting portion; the resisting portion of the crank shaft resists against one end of the deformation sleeve accommodating ring; another end of the deformation sleeve accommodating ring resists against the resisting portions of the deformable sleeve. A rear end of the deformable sleeve is engaged to a chain sleeve. The deformation sleeve accommodating ring is adhesive with sensing sheet.

Abstract: A low-profile and small-size valve to a shut off a flow of fluid in a pipeline includes a frame, a tube, a moving part, a lever, an elastic part, a latch, and a trigger. The tube is movable with the moving part. The lever is rotatable around an axis. The elastic part can push the lever to rotate after the trigger pushes the buckle away from the lever to unlatch the lever and allow rotation. During the rotation of the lever, the lever pulls on the moving part, and the moving part pulls on the tube together to disconnect the tube from the pipe. The valve improves the convenience and efficiency of shutting off a flow of fluid. A pipeline and an immersion cooling system is also disclosed.