Patents by Inventor Chih-an Liu

Chih-an Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096784
    Abstract: Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.
    Type: Application
    Filed: January 3, 2023
    Publication date: March 21, 2024
    Inventors: Meng-Hsien Lin, Hsing-Chih Lin, Ming-Tsong Wang, Min-Feng Kao, Kuan-Hua Lin, Jen-Cheng Liu, Dun-Nian Yaung, Ko Chun Liu
  • Patent number: 11935981
    Abstract: A photo-detecting device includes a first semiconductor layer with a first dopant, a light-absorbing layer, a second semiconductor layer, and a semiconductor contact layer. The second semiconductor layer is located on the first semiconductor layer and has a first region and a second region, the light absorbing layer is located between the first semiconductor layer and the second semiconductor layer and has a third region and a fourth region, the semiconductor contact layer contacts the first region. The first region includes a second dopant and a third dopant, the second region includes second dopant, and the third region includes third dopant. The semiconductor contact layer has a first thickness greater than 50 ? and smaller than 1000 ?.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: March 19, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Chu-Jih Su, Chia-Hsiang Chou, Wei-Chih Peng, Wen-Luh Liao, Chao-Shun Huang, Hsuan-Le Lin, Shih-Chang Lee, Mei Chun Liu, Chen Ou
  • Patent number: 11937370
    Abstract: A base material is provided. A first patterned circuit layer and a second patterned circuit layer are formed on a first surface and a second surface of the base material. A first insulation layer and a metal reflection layer are provided on the first patterned circuit layer and a portion of the first surface exposed by the first patterned circuit layer, wherein the metal reflection layer covers the first insulation layer, and a reflectance of the metal reflection layer is substantially greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer. A first ink layer is formed on the first insulation layer before the metal reflection layer is formed.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: March 19, 2024
    Assignee: UNIFLEX Technology Inc.
    Inventors: Cheng-I Tu, Ying-Hsing Chen, Meng-Huan Chia, Hsin-Ching Su, Yi-Chun Liu, Cheng-Chung Lai, Yuan-Chih Lee
  • Publication number: 20240082245
    Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: November 3, 2023
    Publication date: March 14, 2024
    Inventors: Christine Collins, Bo Fu, Abhishek Gulati, Jens Kort, Matthew Kosloski, Yang Lei, Chih-Wei Lin, Ran Liu, Federico Mensa, Iok Chan NG, Tami Pilot-Matias, David Pugatch, Nancy S. Shulman, Roger Trinh, Rolando M. Viani, Stanley Wang, Zhenzhen Zhang
  • Publication number: 20240090230
    Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Ling Lu, Chen-Jun Wu, Ya-Yun Cheng, Sheng-Chih Lai, Yi-Ching Liu, Yu-Ming Lin, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20240087879
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20240088154
    Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed directly on an upper surface of the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Kong-Beng Thei, Ming Chyi Liu, Shih-Chung Hsiao, Jhih-Bin Chen
  • Publication number: 20240087988
    Abstract: The present disclosure, in some embodiments, relates an integrated chip. The integrated chip includes a substrate. A through-substrate-via (TSV) extends through the substrate. A dielectric liner separates the TSV from the substrate. The dielectric liner is along one or more sidewalls of the substrate. The TSV includes a horizontally extending surface and a protrusion extending outward from the horizontally extending surface. The TSV has a maximum width along the horizontally extending surface.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Hung-Ling Shih, Wei Chuang Wu, Shih Kuang Yang, Hsing-Chih Lin, Jen-Cheng Liu
  • Patent number: 11927400
    Abstract: This disclosure relates to a method for fabricating a vapor chamber. The method includes positioning a capillary structure on a first cover, forming an accommodation space, a flow channel, and a plurality of posts on a first surface of a second cover, covering the first cover with the second cover, positioning the first cover and the second cover such that the plurality of posts are spaced apart from the capillary structure by a distance, and pressure welding the first cover and the second cover so as to form a chamber between the first cover and second cover and a passage connected to the chamber and to pressure weld the plurality of posts with the capillary structure.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: March 12, 2024
    Assignee: COOLER MASTER CO., LTD.
    Inventors: Jen-Chih Cheng, Lei-Lei Liu
  • Patent number: 11908759
    Abstract: A semiconductor device includes a substrate, a body structure and an electronic component. The body structure is disposed above the substrate and includes a semiconductor die, a molding compound, a conductive component and a lower redistribution layer (RDL). The semiconductor die has an active surface. The molding compound encapsulates the semiconductor die and has a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: February 20, 2024
    Assignee: MediaTek Inc.
    Inventors: Nan-Cheng Chen, Che-Ya Chou, Hsing-Chih Liu, Che-Hung Kuo
  • Patent number: 11908767
    Abstract: A semiconductor package structure includes a first redistribution layer, a semiconductor die, a thermal spreader, and a molding material. The semiconductor die is disposed over the first redistribution layer. The thermal spreader is disposed over the semiconductor die. The molding material surrounds the semiconductor die and the thermal spreader.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: February 20, 2024
    Assignee: MEDIATEK INC.
    Inventors: Che-Hung Kuo, Hsing-Chih Liu, Chia-Hao Hsu
  • Patent number: 11908740
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure over a substrate. The semiconductor structure also includes source/drain structures on opposite sides of the gate structure. The semiconductor structure also includes a dielectric layer over the gate structure and the source/drain structures. The semiconductor structure also includes a via plug passing through the dielectric layer and including a first group IV element. The dielectric layer includes a second group IV element, a first compound, and a second compound, and the second compound includes elements in the first compound and the first group IV element.
    Type: Grant
    Filed: November 25, 2022
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Po Hsieh, Su-Hao Liu, Hong-Chih Liu, Jing-Huei Huang, Jie-Huang Huang, Lun-Kuang Tan, Huicheng Chang, Liang-Yin Chen, Kuo-Ju Chen
  • Publication number: 20240036108
    Abstract: A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.
    Type: Application
    Filed: March 30, 2023
    Publication date: February 1, 2024
    Inventors: Chien-Yi Chen, Kao-Chih Liu, Chia Hong Lin, Yu-Ting Lin, Min-Feng Ku
  • Publication number: 20240040701
    Abstract: An integrated circuit (IC) chip assembly includes an integrated circuit (IC) die that includes a first substrate in which plurality of transistors is formed, a first structure that contains a plurality of first metallization components, and a second structure that contains a plurality of second metallization components. The first structure is disposed over a first side of the first substrate. The second structure is disposed over a second side of the first substrate opposite the first side. The chip assembly includes a second substrate bonded to the IC die through the second side. The chip assembly includes a trench that extends through the second substrate and through the second structure of the IC die. Sidewalls of the trench are defined at least in part by one or more protective layers.
    Type: Application
    Filed: March 28, 2023
    Publication date: February 1, 2024
    Inventors: Kao-Chih Liu, Wenmin Hsu, Yu-Ting Lin, Chia Hong Lin, ChienYi Chen
  • Publication number: 20240038587
    Abstract: A semiconductor substrate includes a plurality of transistors. A first structure is disposed over a first side of the semiconductor substrate. The first structure contains a plurality of first metallization components. A carrier substrate is disposed over the first structure. The first structure is located between the carrier substrate and the semiconductor substrate. One or more openings extend through the carrier substrate and expose one or more regions of the first structure to the first side. A second structure is disposed over a second side of the semiconductor substrate opposite the first side. The second structure contains a plurality of second metallization components.
    Type: Application
    Filed: March 30, 2023
    Publication date: February 1, 2024
    Inventors: Kao-Chih Liu, Wenmin Hsu, Hsuan Jung Chiu, Yu-Ting Lin, Chia Hong Lin
  • Patent number: 11885876
    Abstract: An underwater ultrasonic device includes a curvilinear ultrasonic transducer and a plurality of straight linear ultrasonic transducers. The straight linear ultrasonic transducers are disposed with respect to the curvilinear ultrasonic transducer. A first angle is included between the straight linear ultrasonic transducers. One of the curvilinear ultrasonic transducer and the straight linear ultrasonic transducer is configured to transmit a plurality of ultrasonic signals. Another one of the curvilinear ultrasonic transducer and the straight linear ultrasonic transducer is configured to receive a plurality of reflected signals of the ultrasonic signals.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: January 30, 2024
    Assignee: Qisda Corporation
    Inventors: Fu-Sheng Jiang, Chun-Chieh Wang, Yi-Hsiang Chan, Heng-Yi Shiu, Hsin-Chih Liu
  • Patent number: 11885701
    Abstract: A bicycle torque detector includes a crank shaft formed with a first ring section and a second ring section; the first ring section serving for receiving a deformation sleeve accommodating ring and a deformable sleeve; the second ring section serving for receiving a circuit board ring; a circular casing serving to enclose all the crank shaft, the elastic ring, the sleeve, and the circuit board ring; wherein the first ring section of the crank shaft is formed with at least one resisting portion; the deformable sleeve has at least one resisting portion; the resisting portion of the crank shaft resists against one end of the deformation sleeve accommodating ring; another end of the deformation sleeve accommodating ring resists against the resisting portions of the deformable sleeve. A rear end of the deformable sleeve is engaged to a chain sleeve. The deformation sleeve accommodating ring is adhesive with sensing sheet.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: January 30, 2024
    Assignee: NEW KAILUNG GEAR CO., LTD
    Inventor: Jen-Chih Liu
  • Publication number: 20240028807
    Abstract: An embodiment of the present disclosure provides an online integrated microcontroller development tool system. Through the present disclosure, a microcontroller block of a suitable model number is selected according to a client requirement, pins of the microcontroller may be arranged, the microcontroller block with the arranged have been pins is connected to a functional component selected by the client, a corresponding circuit structure is generated, and based on the circuit structure, a microcontroller system hardware description code is generated and output. Different from the conventional development platform, the present disclosure helps clients to develop microcontroller application circuits for different applications through a pin required module, a functional component module and a description code project output module. Thus, purposes of simple operation and saving development time can be achieved.
    Type: Application
    Filed: January 10, 2023
    Publication date: January 25, 2024
    Inventors: CHIEH-SHENG TU, TA-CHIN CHIU, CHUN-MING HUANG, JEN-CHIH LIU
  • Publication number: 20230422525
    Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and a memory die are mounted on a top surface of the bottom substrate in a side-by-side fashion. The logic die may have a thickness not less than 125 micrometers. A connection structure is disposed between the bottom substrate and the top substrate around the logic die and the memory die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and sealing the logic die, the memory die, and the connection structure in the gap.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 28, 2023
    Applicant: MEDIATEK INC.
    Inventors: Ta-Jen Yu, Wen-Chin Tsai, Isabella Song, Che-Hung Kuo, Hsing-Chih Liu, Tai-Yu Chen, Shih-Chin Lin, Wen-Sung Hsu
  • Patent number: 11855189
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate structure, and source/drain structures. The semiconductor fin extends upwardly from the substrate. The gate structure is across the semiconductor fin and includes a high-k dielectric layer over the semiconductor fin, a fluorine-containing work function layer over the high-k dielectric layer and comprising fluorine, a tungsten-containing layer over the fluorine-containing work function layer, and a metal gate electrode over the tungsten-containing layer. The source/drain structures are on the semiconductor fin and at opposite sides of the gate structure.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chandrashekhar P. Savant, Tien-Wei Yu, Ke-Chih Liu, Chia-Ming Tsai